Anup Patel b8fb878aa2 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT ... The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-21 07:56:49 +10:00
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allwinner-a10-pic.h
arm_gic_common.h
arm_gic.h
arm_gicv3_common.h	hw/intc: GICv3 redistributor ITS processing	2021-09-13 21:01:08 +01:00
arm_gicv3_its_common.h	hw/intc: GICv3 ITS register definitions added	2021-09-13 16:07:54 +01:00
arm_gicv3.h
armv7m_nvic.h	arm: Move system PPB container handling to armv7m	2021-09-01 11:08:18 +01:00
aspeed_vic.h
bcm2835_ic.h
bcm2836_control.h
goldfish_pic.h
heathrow_pic.h
i8259.h
ibex_plic.h	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	2021-09-21 07:56:49 +10:00
imx_avic.h
imx_gpcv2.h
intc.h
loongson_liointc.h
m68k_irqc.h
mips_gic.h
ppc-uic.h
realview_gic.h
riscv_aclint.h	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
rx_icu.h
sifive_plic.h	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	2021-09-21 07:56:49 +10:00
xlnx-pmu-iomod-intc.h
xlnx-zynqmp-ipi.h