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qemu-e2k/target/riscv/insn_trans
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Alistair Francis 6baba30ad0 target/riscv: Consolidate RV32/64 16-bit instructions 
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
..
trans_privileged.c.inc riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
trans_rva.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvd.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvf.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvh.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvi.c.inc target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvm.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
trans_rvv.c.inc target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00