Aaron Lindsay 599b71e277 target/arm: Mask PMOVSR writes based on supported counters ... This is an amendment to my earlier patch: commit 7ece99b17e Author: Aaron Lindsay <alindsay@codeaurora.org> Date: Thu Apr 26 11:04:39 2018 +0100 target/arm: Mask PMU register writes based on PMCR_EL0.N Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181010203735.27918-3-aclindsa@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2018-10-16 17:14:55 +01:00
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alpha
arm	target/arm: Mask PMOVSR writes based on supported counters	2018-10-16 17:14:55 +01:00
cris
hppa
i386	target/i386: fix translation for icount mode	2018-10-02 19:09:13 +02:00
lm32
m68k
microblaze
mips	target/mips: Add definition of nanoMIPS I7200 CPU	2018-08-24 17:51:59 +02:00
moxie
nios2
openrisc
ppc	target/ppc/cpu-models: Re-group the 970 CPUs together again	2018-09-25 11:12:25 +10:00
riscv	riscv: remove define cpu_init()	2018-09-05 09:58:38 -07:00
s390x	s390x/kvm: enable AP instruction interpretation for guest	2018-10-12 11:32:18 +02:00
sh4
sparc
tilegx
tricore
unicore32
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00