Bin Meng 59f74489cf hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb ... Commit 28d8c28120 ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which is VIRTIO_NDEV and also used as the value of "riscv,ndev" property in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES should include interrupt source 0 but "riscv,ndev" does not. While we are here, we also fix the comments of platform bus irq range which is now "64 to 96", but should be "64 to 95", introduced since commit 1832b7cb3f ("hw/riscv: virt: Create a platform bus"). Fixes: 28d8c28120 ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221211030829.802437-13-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
boot.c	riscv: re-randomize rng-seed on reboot	2022-10-27 11:34:31 +01:00
Kconfig	hw/riscv: Sort machines Kconfig options in alphabetical order	2023-01-06 10:42:55 +10:00
meson.build
microchip_pfsoc.c	hw/{misc, riscv}: pfsoc: add system controller as unimplemented	2023-01-06 10:42:55 +10:00
numa.c
opentitan.c	hw/riscv/opentitan: add aon_timer base unimpl	2023-01-06 10:42:55 +10:00
riscv_hart.c
shakti_c.c
sifive_e.c
sifive_u.c	hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"	2023-01-06 10:42:55 +10:00
spike.c	hw/riscv: spike: Remove misleading comments	2023-01-06 10:42:55 +10:00
virt.c	hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb	2023-01-06 10:42:55 +10:00