572 lines
15 KiB
C
572 lines
15 KiB
C
/*
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* QEMU 8259 interrupt controller emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "isa.h"
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#include "console.h"
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/* debug PIC */
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//#define DEBUG_PIC
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//#define DEBUG_IRQ_LATENCY
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//#define DEBUG_IRQ_COUNT
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typedef struct PicState {
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uint8_t last_irr; /* edge detection */
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uint8_t irr; /* interrupt request register */
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uint8_t imr; /* interrupt mask register */
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uint8_t isr; /* interrupt service register */
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uint8_t priority_add; /* highest irq priority */
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uint8_t irq_base;
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uint8_t read_reg_select;
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uint8_t poll;
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uint8_t special_mask;
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uint8_t init_state;
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uint8_t auto_eoi;
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uint8_t rotate_on_auto_eoi;
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uint8_t special_fully_nested_mode;
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uint8_t init4; /* true if 4 byte init */
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uint8_t single_mode; /* true if slave pic is not initialized */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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PicState2 *pics_state;
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} PicState;
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struct PicState2 {
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/* 0 is master pic, 1 is slave pic */
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/* XXX: better separation between the two pics */
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PicState pics[2];
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qemu_irq parent_irq;
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void *irq_request_opaque;
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/* IOAPIC callback support */
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SetIRQFunc *alt_irq_func;
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void *alt_irq_opaque;
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};
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#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
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static int irq_level[16];
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#endif
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#ifdef DEBUG_IRQ_COUNT
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static uint64_t irq_count[16];
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#endif
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/* set irq level. If an edge is detected, then the IRR is set to 1 */
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static inline void pic_set_irq1(PicState *s, int irq, int level)
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{
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int mask;
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mask = 1 << irq;
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if (s->elcr & mask) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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s->last_irr |= mask;
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} else {
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s->irr &= ~mask;
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s->last_irr &= ~mask;
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}
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} else {
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/* edge triggered */
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if (level) {
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if ((s->last_irr & mask) == 0)
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s->irr |= mask;
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s->last_irr |= mask;
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} else {
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s->last_irr &= ~mask;
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}
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}
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}
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/* return the highest priority found in mask (highest = smallest
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number). Return 8 if no irq */
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static inline int get_priority(PicState *s, int mask)
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{
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int priority;
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if (mask == 0)
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return 8;
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priority = 0;
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while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
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priority++;
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return priority;
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}
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/* return the pic wanted interrupt. return -1 if none */
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static int pic_get_irq(PicState *s)
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{
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int mask, cur_priority, priority;
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mask = s->irr & ~s->imr;
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priority = get_priority(s, mask);
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if (priority == 8)
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return -1;
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/* compute current priority. If special fully nested mode on the
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master, the IRQ coming from the slave is not taken into account
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for the priority computation. */
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mask = s->isr;
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if (s->special_mask)
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mask &= ~s->imr;
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if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
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mask &= ~(1 << 2);
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cur_priority = get_priority(s, mask);
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if (priority < cur_priority) {
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/* higher priority found: an irq should be generated */
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return (priority + s->priority_add) & 7;
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} else {
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return -1;
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}
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}
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/* raise irq to CPU if necessary. must be called every time the active
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irq may change */
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/* XXX: should not export it, but it is needed for an APIC kludge */
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void pic_update_irq(PicState2 *s)
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{
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int irq2, irq;
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/* first look at slave pic */
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0) {
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/* if irq request by slave pic, signal master PIC */
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pic_set_irq1(&s->pics[0], 2, 1);
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pic_set_irq1(&s->pics[0], 2, 0);
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}
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/* look at requested irq */
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0) {
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#if defined(DEBUG_PIC)
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{
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int i;
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for(i = 0; i < 2; i++) {
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printf("pic%d: imr=%x irr=%x padd=%d\n",
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i, s->pics[i].imr, s->pics[i].irr,
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s->pics[i].priority_add);
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}
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}
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printf("pic: cpu_interrupt\n");
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#endif
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qemu_irq_raise(s->parent_irq);
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}
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/* all targets should do this rather than acking the IRQ in the cpu */
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#if defined(TARGET_MIPS) || defined(TARGET_PPC)
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else {
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qemu_irq_lower(s->parent_irq);
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}
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#endif
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}
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#ifdef DEBUG_IRQ_LATENCY
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int64_t irq_time[16];
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#endif
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static void i8259_set_irq(void *opaque, int irq, int level)
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{
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PicState2 *s = opaque;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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if (level != irq_level[irq]) {
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#if defined(DEBUG_PIC)
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printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
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#endif
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irq_level[irq] = level;
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#ifdef DEBUG_IRQ_COUNT
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if (level == 1)
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irq_count[irq]++;
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#endif
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}
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#endif
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#ifdef DEBUG_IRQ_LATENCY
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if (level) {
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irq_time[irq] = qemu_get_clock(vm_clock);
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}
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#endif
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pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
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/* used for IOAPIC irqs */
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if (s->alt_irq_func)
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s->alt_irq_func(s->alt_irq_opaque, irq, level);
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pic_update_irq(s);
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}
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/* acknowledge interrupt 'irq' */
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static inline void pic_intack(PicState *s, int irq)
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{
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if (s->auto_eoi) {
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if (s->rotate_on_auto_eoi)
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s->priority_add = (irq + 1) & 7;
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} else {
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s->isr |= (1 << irq);
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}
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/* We don't clear a level sensitive interrupt here */
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if (!(s->elcr & (1 << irq)))
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s->irr &= ~(1 << irq);
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}
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int pic_read_irq(PicState2 *s)
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{
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int irq, irq2, intno;
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0) {
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pic_intack(&s->pics[0], irq);
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if (irq == 2) {
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0) {
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pic_intack(&s->pics[1], irq2);
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} else {
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/* spurious IRQ on slave controller */
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irq2 = 7;
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}
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intno = s->pics[1].irq_base + irq2;
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irq = irq2 + 8;
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} else {
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intno = s->pics[0].irq_base + irq;
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}
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} else {
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/* spurious IRQ on host controller */
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irq = 7;
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intno = s->pics[0].irq_base + irq;
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}
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pic_update_irq(s);
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#ifdef DEBUG_IRQ_LATENCY
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printf("IRQ%d latency=%0.3fus\n",
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irq,
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(double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
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#endif
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#if defined(DEBUG_PIC)
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printf("pic_interrupt: irq=%d\n", irq);
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#endif
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return intno;
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}
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static void pic_reset(void *opaque)
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{
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PicState *s = opaque;
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s->last_irr = 0;
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s->irr = 0;
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s->imr = 0;
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s->isr = 0;
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s->priority_add = 0;
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s->irq_base = 0;
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s->read_reg_select = 0;
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s->poll = 0;
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s->special_mask = 0;
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s->init_state = 0;
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s->auto_eoi = 0;
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s->rotate_on_auto_eoi = 0;
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s->special_fully_nested_mode = 0;
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s->init4 = 0;
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s->single_mode = 0;
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/* Note: ELCR is not reset */
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}
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static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PicState *s = opaque;
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int priority, cmd, irq;
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#ifdef DEBUG_PIC
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printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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addr &= 1;
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if (addr == 0) {
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if (val & 0x10) {
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/* init */
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pic_reset(s);
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/* deassert a pending interrupt */
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qemu_irq_lower(s->pics_state->parent_irq);
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s->init_state = 1;
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s->init4 = val & 1;
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s->single_mode = val & 2;
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if (val & 0x08)
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hw_error("level sensitive irq not supported");
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} else if (val & 0x08) {
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if (val & 0x04)
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s->poll = 1;
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if (val & 0x02)
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s->read_reg_select = val & 1;
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if (val & 0x40)
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s->special_mask = (val >> 5) & 1;
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} else {
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cmd = val >> 5;
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switch(cmd) {
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case 0:
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case 4:
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s->rotate_on_auto_eoi = cmd >> 2;
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break;
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case 1: /* end of interrupt */
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case 5:
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priority = get_priority(s, s->isr);
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if (priority != 8) {
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irq = (priority + s->priority_add) & 7;
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s->isr &= ~(1 << irq);
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if (cmd == 5)
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s->priority_add = (irq + 1) & 7;
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pic_update_irq(s->pics_state);
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}
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break;
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case 3:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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pic_update_irq(s->pics_state);
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break;
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case 6:
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s->priority_add = (val + 1) & 7;
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pic_update_irq(s->pics_state);
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break;
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case 7:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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s->priority_add = (irq + 1) & 7;
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pic_update_irq(s->pics_state);
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break;
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default:
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/* no operation */
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break;
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}
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}
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} else {
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switch(s->init_state) {
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case 0:
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/* normal mode */
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s->imr = val;
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pic_update_irq(s->pics_state);
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break;
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case 1:
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s->irq_base = val & 0xf8;
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s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
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break;
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case 2:
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if (s->init4) {
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s->init_state = 3;
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} else {
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s->init_state = 0;
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}
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break;
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case 3:
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s->special_fully_nested_mode = (val >> 4) & 1;
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s->auto_eoi = (val >> 1) & 1;
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s->init_state = 0;
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break;
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}
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}
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}
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static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
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{
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int ret;
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ret = pic_get_irq(s);
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if (ret >= 0) {
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if (addr1 >> 7) {
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s->pics_state->pics[0].isr &= ~(1 << 2);
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s->pics_state->pics[0].irr &= ~(1 << 2);
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}
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s->irr &= ~(1 << ret);
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s->isr &= ~(1 << ret);
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if (addr1 >> 7 || ret != 2)
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pic_update_irq(s->pics_state);
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} else {
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ret = 0x07;
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pic_update_irq(s->pics_state);
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}
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return ret;
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}
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static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
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{
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PicState *s = opaque;
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unsigned int addr;
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int ret;
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addr = addr1;
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addr &= 1;
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if (s->poll) {
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ret = pic_poll_read(s, addr1);
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s->poll = 0;
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} else {
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if (addr == 0) {
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if (s->read_reg_select)
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ret = s->isr;
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else
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ret = s->irr;
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} else {
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ret = s->imr;
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}
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}
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#ifdef DEBUG_PIC
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printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
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#endif
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return ret;
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}
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/* memory mapped interrupt status */
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/* XXX: may be the same than pic_read_irq() */
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uint32_t pic_intack_read(PicState2 *s)
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{
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int ret;
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ret = pic_poll_read(&s->pics[0], 0x00);
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if (ret == 2)
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ret = pic_poll_read(&s->pics[1], 0x80) + 8;
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/* Prepare for ISR read */
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s->pics[0].read_reg_select = 1;
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return ret;
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}
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static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PicState *s = opaque;
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s->elcr = val & s->elcr_mask;
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}
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static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
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{
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PicState *s = opaque;
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return s->elcr;
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}
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static void pic_save(QEMUFile *f, void *opaque)
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{
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PicState *s = opaque;
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qemu_put_8s(f, &s->last_irr);
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qemu_put_8s(f, &s->irr);
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qemu_put_8s(f, &s->imr);
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qemu_put_8s(f, &s->isr);
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qemu_put_8s(f, &s->priority_add);
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qemu_put_8s(f, &s->irq_base);
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qemu_put_8s(f, &s->read_reg_select);
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qemu_put_8s(f, &s->poll);
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qemu_put_8s(f, &s->special_mask);
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qemu_put_8s(f, &s->init_state);
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qemu_put_8s(f, &s->auto_eoi);
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qemu_put_8s(f, &s->rotate_on_auto_eoi);
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qemu_put_8s(f, &s->special_fully_nested_mode);
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qemu_put_8s(f, &s->init4);
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qemu_put_8s(f, &s->single_mode);
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qemu_put_8s(f, &s->elcr);
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}
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static int pic_load(QEMUFile *f, void *opaque, int version_id)
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{
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PicState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_8s(f, &s->last_irr);
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qemu_get_8s(f, &s->irr);
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qemu_get_8s(f, &s->imr);
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qemu_get_8s(f, &s->isr);
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qemu_get_8s(f, &s->priority_add);
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qemu_get_8s(f, &s->irq_base);
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qemu_get_8s(f, &s->read_reg_select);
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qemu_get_8s(f, &s->poll);
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qemu_get_8s(f, &s->special_mask);
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qemu_get_8s(f, &s->init_state);
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qemu_get_8s(f, &s->auto_eoi);
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qemu_get_8s(f, &s->rotate_on_auto_eoi);
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qemu_get_8s(f, &s->special_fully_nested_mode);
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qemu_get_8s(f, &s->init4);
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qemu_get_8s(f, &s->single_mode);
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qemu_get_8s(f, &s->elcr);
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return 0;
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}
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/* XXX: add generic master/slave system */
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static void pic_init1(int io_addr, int elcr_addr, PicState *s)
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{
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register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
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register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
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if (elcr_addr >= 0) {
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|
register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
|
|
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
|
|
}
|
|
register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
|
|
qemu_register_reset(pic_reset, s);
|
|
}
|
|
|
|
void pic_info(void)
|
|
{
|
|
int i;
|
|
PicState *s;
|
|
|
|
if (!isa_pic)
|
|
return;
|
|
|
|
for(i=0;i<2;i++) {
|
|
s = &isa_pic->pics[i];
|
|
term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
|
|
i, s->irr, s->imr, s->isr, s->priority_add,
|
|
s->irq_base, s->read_reg_select, s->elcr,
|
|
s->special_fully_nested_mode);
|
|
}
|
|
}
|
|
|
|
void irq_info(void)
|
|
{
|
|
#ifndef DEBUG_IRQ_COUNT
|
|
term_printf("irq statistic code not compiled.\n");
|
|
#else
|
|
int i;
|
|
int64_t count;
|
|
|
|
term_printf("IRQ statistics:\n");
|
|
for (i = 0; i < 16; i++) {
|
|
count = irq_count[i];
|
|
if (count > 0)
|
|
term_printf("%2d: %" PRId64 "\n", i, count);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
qemu_irq *i8259_init(qemu_irq parent_irq)
|
|
{
|
|
PicState2 *s;
|
|
|
|
s = qemu_mallocz(sizeof(PicState2));
|
|
if (!s)
|
|
return NULL;
|
|
pic_init1(0x20, 0x4d0, &s->pics[0]);
|
|
pic_init1(0xa0, 0x4d1, &s->pics[1]);
|
|
s->pics[0].elcr_mask = 0xf8;
|
|
s->pics[1].elcr_mask = 0xde;
|
|
s->parent_irq = parent_irq;
|
|
s->pics[0].pics_state = s;
|
|
s->pics[1].pics_state = s;
|
|
isa_pic = s;
|
|
return qemu_allocate_irqs(i8259_set_irq, s, 16);
|
|
}
|
|
|
|
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
|
void *alt_irq_opaque)
|
|
{
|
|
s->alt_irq_func = alt_irq_func;
|
|
s->alt_irq_opaque = alt_irq_opaque;
|
|
}
|