361 lines
9.9 KiB
C
361 lines
9.9 KiB
C
#if !defined (__MIPS_CPU_H__)
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#define __MIPS_CPU_H__
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE EM_MIPS
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#include "config.h"
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#include "mips-defs.h"
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#include "cpu-defs.h"
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#include "softfloat.h"
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// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
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// XXX: move that elsewhere
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#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
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typedef unsigned char uint_fast8_t;
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typedef unsigned int uint_fast16_t;
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#endif
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typedef union fpr_t fpr_t;
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union fpr_t {
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float64 fd; /* ieee double precision */
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float32 fs[2];/* ieee single precision */
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uint64_t d; /* binary double fixed-point */
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uint32_t w[2]; /* binary single fixed-point */
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};
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/* define FP_ENDIAN_IDX to access the same location
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* in the fpr_t union regardless of the host endianess
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*/
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#if defined(WORDS_BIGENDIAN)
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# define FP_ENDIAN_IDX 1
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#else
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# define FP_ENDIAN_IDX 0
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#endif
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#if defined(MIPS_USES_R4K_TLB)
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typedef struct tlb_t tlb_t;
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struct tlb_t {
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target_ulong VPN;
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uint32_t PageMask;
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uint_fast8_t ASID;
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uint_fast16_t G:1;
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uint_fast16_t C0:3;
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uint_fast16_t C1:3;
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uint_fast16_t V0:1;
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uint_fast16_t V1:1;
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uint_fast16_t D0:1;
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uint_fast16_t D1:1;
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target_ulong PFN[2];
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};
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#endif
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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/* General integer registers */
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target_ulong gpr[32];
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/* Special registers */
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target_ulong PC;
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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target_ulong t0;
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target_ulong t1;
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target_ulong t2;
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#endif
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target_ulong HI, LO;
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/* Floating point registers */
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fpr_t fpr[32];
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#ifndef USE_HOST_FLOAT_REGS
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fpr_t ft0;
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fpr_t ft1;
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fpr_t ft2;
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#endif
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float_status fp_status;
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0;
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#define FCR0_F64 22
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#define FCR0_L 21
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#define FCR0_W 20
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#define FCR0_3D 19
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#define FCR0_PS 18
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#define FCR0_D 17
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#define FCR0_S 16
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#define FCR0_PRID 8
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#define FCR0_REV 0
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/* fcsr */
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uint32_t fcr31;
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#define SET_FP_COND(num,env) do { (env->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
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#define CLEAR_FP_COND(num,env) do { (env->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
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#define IS_FP_COND_SET(num,env) (((env->fcr31) & ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23)))) != 0)
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#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
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#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
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#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
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#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
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#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
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#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
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#define FP_INEXACT 1
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#define FP_UNDERFLOW 2
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#define FP_OVERFLOW 4
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#define FP_DIV0 8
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#define FP_INVALID 16
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#define FP_UNIMPLEMENTED 32
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#if defined(MIPS_USES_R4K_TLB)
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tlb_t tlb[MIPS_TLB_MAX];
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uint32_t tlb_in_use;
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uint32_t nb_tlb;
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#endif
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int32_t CP0_Index;
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int32_t CP0_Random;
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target_ulong CP0_EntryLo0;
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target_ulong CP0_EntryLo1;
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target_ulong CP0_Context;
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int32_t CP0_PageMask;
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int32_t CP0_PageGrain;
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int32_t CP0_Wired;
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int32_t CP0_HWREna;
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target_ulong CP0_BadVAddr;
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int32_t CP0_Count;
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target_ulong CP0_EntryHi;
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int32_t CP0_Compare;
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int32_t CP0_Status;
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#define CP0St_CU3 31
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#define CP0St_CU2 30
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#define CP0St_CU1 29
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#define CP0St_CU0 28
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#define CP0St_RP 27
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#define CP0St_FR 26
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#define CP0St_RE 25
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#define CP0St_MX 24
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#define CP0St_PX 23
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#define CP0St_BEV 22
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#define CP0St_TS 21
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#define CP0St_SR 20
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#define CP0St_NMI 19
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#define CP0St_IM 8
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#define CP0St_KX 7
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#define CP0St_SX 6
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#define CP0St_UX 5
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#define CP0St_UM 4
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#define CP0St_R0 3
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#define CP0St_ERL 2
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#define CP0St_EXL 1
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#define CP0St_IE 0
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int32_t CP0_IntCtl;
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int32_t CP0_SRSCtl;
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int32_t CP0_SRSMap;
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int32_t CP0_Cause;
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#define CP0Ca_BD 31
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#define CP0Ca_TI 30
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#define CP0Ca_CE 28
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#define CP0Ca_DC 27
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#define CP0Ca_PCI 26
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#define CP0Ca_IV 23
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#define CP0Ca_WP 22
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#define CP0Ca_IP 8
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#define CP0Ca_IP_mask 0x0000FF00
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#define CP0Ca_EC 2
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target_ulong CP0_EPC;
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int32_t CP0_PRid;
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int32_t CP0_EBase;
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int32_t CP0_Config0;
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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#define CP0C0_AR 10
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#define CP0C0_MT 7
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#define CP0C0_VI 3
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#define CP0C0_K0 0
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int32_t CP0_Config1;
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#define CP0C1_M 31
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#define CP0C1_MMU 25
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#define CP0C1_IS 22
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#define CP0C1_IL 19
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#define CP0C1_IA 16
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#define CP0C1_DS 13
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#define CP0C1_DL 10
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#define CP0C1_DA 7
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#define CP0C1_C2 6
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#define CP0C1_MD 5
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#define CP0C1_PC 4
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#define CP0C1_WR 3
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#define CP0C1_CA 2
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#define CP0C1_EP 1
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#define CP0C1_FP 0
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int32_t CP0_Config2;
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#define CP0C2_M 31
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#define CP0C2_TU 28
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#define CP0C2_TS 24
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#define CP0C2_TL 20
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#define CP0C2_TA 16
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#define CP0C2_SU 12
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#define CP0C2_SS 8
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#define CP0C2_SL 4
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#define CP0C2_SA 0
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int32_t CP0_Config3;
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#define CP0C3_M 31
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#define CP0C3_DSPP 10
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#define CP0C3_LPA 7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP 4
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#define CP0C3_MT 2
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#define CP0C3_SM 1
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#define CP0C3_TL 0
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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target_ulong CP0_LLAddr;
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target_ulong CP0_WatchLo;
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int32_t CP0_WatchHi;
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target_ulong CP0_XContext;
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int32_t CP0_Framemask;
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int32_t CP0_Debug;
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#define CPDB_DBD 31
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#define CP0DB_DM 30
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#define CP0DB_LSNM 28
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#define CP0DB_Doze 27
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#define CP0DB_Halt 26
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#define CP0DB_CNT 25
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#define CP0DB_IBEP 24
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#define CP0DB_DBEP 21
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#define CP0DB_IEXI 20
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#define CP0DB_VER 15
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#define CP0DB_DEC 10
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#define CP0DB_SSt 8
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#define CP0DB_DINT 5
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#define CP0DB_DIB 4
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#define CP0DB_DDBS 3
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#define CP0DB_DDBL 2
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#define CP0DB_DBp 1
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#define CP0DB_DSS 0
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target_ulong CP0_DEPC;
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int32_t CP0_Performance0;
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int32_t CP0_TagLo;
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int32_t CP0_DataLo;
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int32_t CP0_TagHi;
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int32_t CP0_DataHi;
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target_ulong CP0_ErrorEPC;
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int32_t CP0_DESAVE;
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/* Qemu */
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int interrupt_request;
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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int user_mode_only; /* user mode only simulation */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x007F
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#define MIPS_HFLAG_MODE 0x001F /* execution modes */
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#define MIPS_HFLAG_UM 0x0001 /* user mode */
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#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
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#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
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#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
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/* If translation is interrupted between the branch instruction and
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* the delay slot, record what type of branch it is so that we can
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* resume translation properly. It might be possible to reduce
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* this from three bits to two. */
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#define MIPS_HFLAG_BMASK 0x0380
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#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0180 /* Likely branch */
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#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
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target_ulong btarget; /* Jump / branch target */
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int bcond; /* Branch condition (if needed) */
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int halted; /* TRUE if the CPU is in suspend state */
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int SYNCI_Step; /* Address step size for SYNCI */
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int CCRes; /* Cycle count resolution/divisor */
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int Status_rw_bitmask; /* Read/write bits in CP0_Status */
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#if defined(CONFIG_USER_ONLY)
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target_ulong tls_value;
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#else
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void *irq[8];
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#endif
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CPU_COMMON
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int ram_size;
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const char *kernel_filename;
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const char *kernel_cmdline;
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const char *initrd_filename;
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struct QEMUTimer *timer; /* Internal timer */
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};
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typedef struct mips_def_t mips_def_t;
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int mips_find_by_name (const unsigned char *name, mips_def_t **def);
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void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
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int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
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#include "cpu-all.h"
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/* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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/* 1 bit to define user level / supervisor access */
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ACCESS_USER = 0x00,
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ACCESS_SUPER = 0x01,
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/* 1 bit to indicate direction */
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ACCESS_STORE = 0x02,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */
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ACCESS_INT = 0x20, /* Integer load/store access */
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ACCESS_FLOAT = 0x30, /* floating point load/store access */
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};
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/* Exceptions */
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enum {
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EXCP_NONE = -1,
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EXCP_RESET = 0,
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EXCP_SRESET,
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EXCP_DSS,
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EXCP_DINT,
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EXCP_NMI,
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EXCP_MCHECK,
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EXCP_EXT_INTERRUPT,
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EXCP_DFWATCH,
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EXCP_DIB, /* 8 */
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EXCP_IWATCH,
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EXCP_AdEL,
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EXCP_AdES,
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EXCP_TLBF,
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EXCP_IBE,
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EXCP_DBp,
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EXCP_SYSCALL,
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EXCP_BREAK, /* 16 */
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EXCP_CpU,
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EXCP_RI,
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EXCP_OVERFLOW,
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EXCP_TRAP,
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EXCP_FPE,
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EXCP_DDBS,
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EXCP_DWATCH,
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EXCP_LAE, /* 24 */
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EXCP_SAE,
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EXCP_LTLBL,
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EXCP_TLBL,
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EXCP_TLBS,
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EXCP_DBE,
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EXCP_DDBL,
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EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
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/* may change privilege level */
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EXCP_BRANCH = 0x108, /* branch instruction */
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EXCP_ERET = 0x10C, /* return from interrupt */
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EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
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EXCP_FLUSH = 0x109,
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};
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int cpu_mips_exec(CPUMIPSState *s);
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CPUMIPSState *cpu_mips_init(void);
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uint32_t cpu_mips_get_clock (void);
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#endif /* !defined (__MIPS_CPU_H__) */
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