446587a914
For SSE-300, the SYSINFO register block has two new registers: * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3; since the SSE-300 can only be configured with a single CPU it is always zero * IIDR is the subsystem implementation identity register; its value is set by the SoC integrator, so we plumb this in from the armsse.c code as we do with SYS_VERSION and SYS_CONFIG Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
188 lines
5.0 KiB
C
188 lines
5.0 KiB
C
/*
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* ARM IoTKit system information block
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "system information block" which is part of the
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* Arm IoTKit and documented in
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* https://developer.arm.com/documentation/ecm0601256/latest
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* It consists of 2 read-only version/config registers, plus the
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* usual ID registers.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/iotkit-sysinfo.h"
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#include "hw/qdev-properties.h"
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#include "hw/arm/armsse-version.h"
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REG32(SYS_VERSION, 0x0)
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REG32(SYS_CONFIG, 0x4)
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REG32(SYS_CONFIG1, 0x8)
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REG32(IIDR, 0xfc8)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int sysinfo_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static const int sysinfo_sse300_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x58, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IoTKitSysInfo *s = IOTKIT_SYSINFO(opaque);
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uint64_t r;
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switch (offset) {
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case A_SYS_VERSION:
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r = s->sys_version;
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break;
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case A_SYS_CONFIG:
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r = s->sys_config;
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break;
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case A_SYS_CONFIG1:
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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return 0;
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break;
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default:
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goto bad_read;
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}
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break;
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case A_IIDR:
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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return s->iidr;
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break;
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default:
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goto bad_read;
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}
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break;
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case A_PID4 ... A_CID3:
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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r = sysinfo_sse300_id[(offset - A_PID4) / 4];
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break;
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default:
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r = sysinfo_id[(offset - A_PID4) / 4];
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break;
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}
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break;
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default:
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bad_read:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysInfo read: bad offset %x\n", (int)offset);
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r = 0;
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break;
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}
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trace_iotkit_sysinfo_read(offset, r, size);
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return r;
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}
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static void iotkit_sysinfo_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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trace_iotkit_sysinfo_write(offset, value, size);
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysInfo: write to RO offset 0x%x\n", (int)offset);
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}
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static const MemoryRegionOps iotkit_sysinfo_ops = {
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.read = iotkit_sysinfo_read,
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.write = iotkit_sysinfo_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* byte/halfword accesses are just zero-padded on reads and writes */
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static Property iotkit_sysinfo_props[] = {
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DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0),
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DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0),
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DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0),
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DEFINE_PROP_UINT32("IIDR", IoTKitSysInfo, iidr, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void iotkit_sysinfo_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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IoTKitSysInfo *s = IOTKIT_SYSINFO(obj);
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memory_region_init_io(&s->iomem, obj, &iotkit_sysinfo_ops,
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s, "iotkit-sysinfo", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void iotkit_sysinfo_realize(DeviceState *dev, Error **errp)
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{
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IoTKitSysInfo *s = IOTKIT_SYSINFO(dev);
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if (!armsse_version_valid(s->sse_version)) {
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error_setg(errp, "invalid sse-version value %d", s->sse_version);
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return;
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}
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}
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static void iotkit_sysinfo_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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/*
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* This device has no guest-modifiable state and so it
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* does not need a reset function or VMState.
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*/
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dc->realize = iotkit_sysinfo_realize;
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device_class_set_props(dc, iotkit_sysinfo_props);
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}
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static const TypeInfo iotkit_sysinfo_info = {
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.name = TYPE_IOTKIT_SYSINFO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IoTKitSysInfo),
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.instance_init = iotkit_sysinfo_init,
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.class_init = iotkit_sysinfo_class_init,
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};
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static void iotkit_sysinfo_register_types(void)
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{
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type_register_static(&iotkit_sysinfo_info);
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}
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type_init(iotkit_sysinfo_register_types);
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