5b0f170a8a
This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). We can also adjust the number of banks now that we have control on ppc4xx_sdram_init(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20220809153904.485018-7-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
/*
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* QEMU PowerPC 405 shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC405_H
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#define PPC405_H
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#include "qom/object.h"
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#include "hw/ppc/ppc4xx.h"
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#define PPC405EP_SDRAM_BASE 0x00000000
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#define PPC405EP_NVRAM_BASE 0xF0000000
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#define PPC405EP_FPGA_BASE 0xF0300000
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#define PPC405EP_SRAM_BASE 0xFFF00000
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#define PPC405EP_SRAM_SIZE (512 * KiB)
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#define PPC405EP_FLASH_BASE 0xFFF80000
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/* Bootinfo as set-up by u-boot */
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typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
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struct ppc4xx_bd_info_t {
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uint32_t bi_memstart;
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uint32_t bi_memsize;
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uint32_t bi_flashstart;
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uint32_t bi_flashsize;
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uint32_t bi_flashoffset; /* 0x10 */
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uint32_t bi_sramstart;
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uint32_t bi_sramsize;
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uint32_t bi_bootflags;
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uint32_t bi_ipaddr; /* 0x20 */
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uint8_t bi_enetaddr[6];
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uint16_t bi_ethspeed;
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uint32_t bi_intfreq;
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uint32_t bi_busfreq; /* 0x30 */
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uint32_t bi_baudrate;
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uint8_t bi_s_version[4];
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uint8_t bi_r_version[32];
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uint32_t bi_procfreq;
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uint32_t bi_plb_busfreq;
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uint32_t bi_pci_busfreq;
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uint8_t bi_pci_enetaddr[6];
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uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
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uint32_t bi_opbfreq;
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uint32_t bi_iic_fast[2];
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};
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#define TYPE_PPC405_SOC "ppc405-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
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struct Ppc405SoCState {
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/* Private */
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DeviceState parent_obj;
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/* Public */
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MemoryRegion ram_banks[2];
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hwaddr ram_bases[2], ram_sizes[2];
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bool do_dram_init;
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MemoryRegion *dram_mr;
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hwaddr ram_size;
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uint32_t sysclk;
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PowerPCCPU *cpu;
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DeviceState *uic;
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};
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/* PowerPC 405 core */
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ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
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void ppc4xx_plb_init(CPUPPCState *env);
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void ppc405_ebc_init(CPUPPCState *env);
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#endif /* PPC405_H */
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