qemu-e2k/include
Peter Maydell a4716fd8d7 Second RISC-V PR for QEMU 6.1
- Update the PLIC and CLINT DT bindings
  - Improve documentation for RISC-V machines
  - Support direct kernel boot for microchip_pfsoc
  - Fix WFI exception behaviour
  - Improve CSR printing
  - Initial support for the experimental Bit Manip extension
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging

Second RISC-V PR for QEMU 6.1

 - Update the PLIC and CLINT DT bindings
 - Improve documentation for RISC-V machines
 - Support direct kernel boot for microchip_pfsoc
 - Fix WFI exception behaviour
 - Improve CSR printing
 - Initial support for the experimental Bit Manip extension

# gpg: Signature made Tue 08 Jun 2021 01:28:27 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits)
  target/riscv: rvb: add b-ext version cpu option
  target/riscv: rvb: support and turn on B-extension from command line
  target/riscv: rvb: add/shift with prefix zero-extend
  target/riscv: rvb: address calculation
  target/riscv: rvb: generalized or-combine
  target/riscv: rvb: generalized reverse
  target/riscv: rvb: rotate (left/right)
  target/riscv: rvb: shift ones
  target/riscv: rvb: single-bit instructions
  target/riscv: add gen_shifti() and gen_shiftiw() helper functions
  target/riscv: rvb: sign-extend instructions
  target/riscv: rvb: min/max instructions
  target/riscv: rvb: pack two words into one register
  target/riscv: rvb: logic-with-negate
  target/riscv: rvb: count bits set
  target/riscv: rvb: count leading/trailing zeros
  target/riscv: reformat @sh format encoding for B-extension
  target/riscv: Pass the same value to oprsz and maxsz.
  target/riscv/pmp: Add assert for ePMP operations
  target/riscv: Dump CSR mscratch/sscratch/satp
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-08 13:54:23 +01:00
..
authz Prefer 'on' | 'off' over 'yes' | 'no' for bool options 2021-01-29 17:07:53 +00:00
block vl: plumb keyval-based options into -readconfig 2021-06-04 13:50:04 +02:00
chardev chardev: Fix yank with the chardev-change case 2021-04-01 15:27:44 +04:00
crypto crypto: add reload for QCryptoTLSCredsClass 2021-03-23 08:48:21 +01:00
disas Drop the deprecated lm32 target 2021-05-12 18:20:25 +02:00
exec docs: fix broken reference 2021-06-05 21:15:22 +02:00
fpu softfloat: Convert modrem operations to FloatParts 2021-06-03 14:09:02 -07:00
hw Second RISC-V PR for QEMU 6.1 2021-06-08 13:54:23 +01:00
io io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpers 2021-02-10 09:23:28 +00:00
libdecnumber
migration cpu: Move CPUClass::vmsd to SysemuCPUOps 2021-05-26 15:33:59 -07:00
monitor misc: Correct relative include path 2021-06-05 21:10:42 +02:00
net net: Added SetSteeringEBPF method for NetClientState. 2021-06-04 15:25:46 +08:00
qapi vl: plumb keyval-based options into -readconfig 2021-06-04 13:50:04 +02:00
qemu qemu-config: parse configuration files to a QDict 2021-06-04 13:50:01 +02:00
qom qom: move user_creatable_add_opts logic to vl.c and QAPIfy it 2021-03-19 10:18:17 +01:00
scsi scsi: inline sg_io_sense_from_errno() into the callers. 2021-03-06 11:42:56 +01:00
semihosting semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
standard-headers headers: Add udmabuf.h 2021-05-27 12:06:37 +02:00
sysemu hvf: Introduce hvf vcpu struct 2021-06-03 16:43:27 +01:00
tcg accel/tcg: Reduce 'exec/tb-context.h' inclusion 2021-05-26 15:31:45 -07:00
ui ui/pixman: Add qemu_pixman_to_drm_format() 2021-05-27 12:07:37 +02:00
user
elf.h Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00
glib-compat.h configure: bump min required glib version to 2.56 2021-06-02 09:11:32 +02:00
qemu-common.h qemu-common.h: Update copyright string to 2021 2021-03-09 22:19:24 +01:00
qemu-io.h
trace-tcg.h