b2097003ec
Introduce a max_cpus per-machine variable, allowing individual boards to limit it's number of CPUs. Check requested number of CPUs in setup code and exit if it exceeds the supported number for the machine. This also renders the static MAX_CPUS check obsolete, so remove this from vl.c. Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5443 c046a42c-6fe2-441c-8c8c-71466251a162
767 lines
22 KiB
C
767 lines
22 KiB
C
/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "nvram.h"
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#include "pc.h"
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#include "fdc.h"
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#include "net.h"
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#include "sysemu.h"
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#include "isa.h"
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#include "pci.h"
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#include "ppc.h"
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#include "boards.h"
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#include "qemu-log.h"
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define MAX_IDE_BUS 2
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#define BIOS_FILENAME "ppc_rom.bin"
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \
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} else { \
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printf("%s : " fmt, __func__ , ##args); \
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} \
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} while (0)
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \
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} \
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} while (0)
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#else
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#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 13, 13 };
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#define NE2000_NB_MAX 6
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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//static PITState *pit;
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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/* Speaker port 0x61 */
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int speaker_data_on;
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int dummy_refresh_clock;
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static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
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{
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#if 0
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speaker_data_on = (val >> 1) & 1;
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pit_set_gate(pit, 2, val & 1);
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#endif
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}
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static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
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{
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#if 0
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int out;
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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dummy_refresh_clock ^= 1;
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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(dummy_refresh_clock << 4);
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#endif
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return 0;
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}
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/* PCI intack register */
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/* Read-only register (?) */
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static void _PPC_intack_write (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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}
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static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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if (addr == 0xBFFFFFF0)
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retval = pic_intack_read(isa_pic);
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// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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return retval;
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}
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
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{
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return _PPC_intack_read(addr);
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}
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap16(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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}
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap32(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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}
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static CPUWriteMemoryFunc *PPC_intack_write[] = {
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&_PPC_intack_write,
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&_PPC_intack_write,
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&_PPC_intack_write,
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};
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static CPUReadMemoryFunc *PPC_intack_read[] = {
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&PPC_intack_readb,
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&PPC_intack_readw,
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&PPC_intack_readl,
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};
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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}
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static void PPC_XCSR_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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}
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static void PPC_XCSR_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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}
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap16(retval);
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#endif
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return retval;
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}
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval);
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#endif
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return retval;
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}
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static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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&PPC_XCSR_writeb,
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&PPC_XCSR_writew,
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&PPC_XCSR_writel,
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};
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static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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&PPC_XCSR_readb,
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&PPC_XCSR_readw,
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&PPC_XCSR_readl,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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m48t59_t *nvram;
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uint8_t state;
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uint8_t syscontrol;
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uint8_t fake_io[2];
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int contiguous_map;
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int endian;
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} sysctrl_t;
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enum {
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STATE_HARDFILE = 0x01,
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};
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
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val);
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sysctrl->fake_io[addr - 0x0398] = val;
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}
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static uint32_t PREP_io_read (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
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sysctrl->fake_io[addr - 0x0398]);
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return sysctrl->fake_io[addr - 0x0398];
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}
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
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addr - PPC_IO_BASE, val);
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) {
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qemu_irq_raise(sysctrl->reset_irq);
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} else {
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qemu_irq_lower(sysctrl->reset_irq);
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}
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/* Check LE mode */
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if (val & 0x02) {
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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}
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break;
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case 0x0800:
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802:
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803:
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/* Motorola base module status register : read-only */
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break;
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case 0x0808:
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/* Hardfile light register */
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if (val & 1)
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sysctrl->state |= STATE_HARDFILE;
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else
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sysctrl->state &= ~STATE_HARDFILE;
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
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case 0x0814:
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C:
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val);
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break;
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}
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}
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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retval = 0x00;
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break;
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case 0x0800:
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */
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break;
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case 0x0802:
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
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break;
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case 0x0803:
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */
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break;
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case 0x080C:
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810:
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
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break;
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case 0x0814:
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/* L2 invalidate: don't care */
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break;
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case 0x0818:
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C:
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol;
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break;
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case 0x0823:
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/* */
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retval = 0x03; /* no L2 cache */
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break;
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case 0x0850:
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/* I/O map type register */
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retval = sysctrl->contiguous_map;
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break;
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default:
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printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
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break;
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}
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
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addr - PPC_IO_BASE, retval);
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return retval;
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}
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static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
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target_phys_addr_t
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addr)
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{
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if (sysctrl->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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return addr;
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}
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static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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cpu_outb(NULL, addr, value);
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}
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static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inb(NULL, addr);
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return ret;
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}
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static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outw(NULL, addr, value);
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}
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static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inw(NULL, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outl(NULL, addr, value);
|
|
}
|
|
|
|
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
sysctrl_t *sysctrl = opaque;
|
|
uint32_t ret;
|
|
|
|
addr = prep_IO_address(sysctrl, addr);
|
|
ret = cpu_inl(NULL, addr);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
ret = bswap32(ret);
|
|
#endif
|
|
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
CPUWriteMemoryFunc *PPC_prep_io_write[] = {
|
|
&PPC_prep_io_writeb,
|
|
&PPC_prep_io_writew,
|
|
&PPC_prep_io_writel,
|
|
};
|
|
|
|
CPUReadMemoryFunc *PPC_prep_io_read[] = {
|
|
&PPC_prep_io_readb,
|
|
&PPC_prep_io_readw,
|
|
&PPC_prep_io_readl,
|
|
};
|
|
|
|
#define NVRAM_SIZE 0x2000
|
|
|
|
/* PowerPC PREP hardware initialisation */
|
|
static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
|
|
const char *boot_device, DisplayState *ds,
|
|
const char *kernel_filename,
|
|
const char *kernel_cmdline,
|
|
const char *initrd_filename,
|
|
const char *cpu_model)
|
|
{
|
|
CPUState *env = NULL, *envs[MAX_CPUS];
|
|
char buf[1024];
|
|
nvram_t nvram;
|
|
m48t59_t *m48t59;
|
|
int PPC_io_memory;
|
|
int linux_boot, i, nb_nics1, bios_size;
|
|
unsigned long bios_offset;
|
|
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
|
|
PCIBus *pci_bus;
|
|
qemu_irq *i8259;
|
|
int ppc_boot_device;
|
|
int index;
|
|
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
|
BlockDriverState *fd[MAX_FD];
|
|
|
|
sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
|
if (sysctrl == NULL)
|
|
return;
|
|
|
|
linux_boot = (kernel_filename != NULL);
|
|
|
|
/* init CPUs */
|
|
if (cpu_model == NULL)
|
|
cpu_model = "default";
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
env = cpu_init(cpu_model);
|
|
if (!env) {
|
|
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
|
exit(1);
|
|
}
|
|
if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
|
/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
|
cpu_ppc_tb_init(env, 7812500UL);
|
|
} else {
|
|
/* Set time-base frequency to 100 Mhz */
|
|
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
|
|
}
|
|
qemu_register_reset(&cpu_ppc_reset, env);
|
|
envs[i] = env;
|
|
}
|
|
|
|
/* allocate RAM */
|
|
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
|
|
|
/* allocate and load BIOS */
|
|
bios_offset = ram_size + vga_ram_size;
|
|
if (bios_name == NULL)
|
|
bios_name = BIOS_FILENAME;
|
|
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
|
|
bios_size = load_image(buf, phys_ram_base + bios_offset);
|
|
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
|
cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
|
exit(1);
|
|
}
|
|
if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
|
|
cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
|
|
}
|
|
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
cpu_register_physical_memory((uint32_t)(-bios_size),
|
|
bios_size, bios_offset | IO_MEM_ROM);
|
|
|
|
if (linux_boot) {
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
|
/* now we can load the kernel */
|
|
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
|
|
if (kernel_size < 0) {
|
|
cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
|
kernel_filename);
|
|
exit(1);
|
|
}
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
initrd_base = INITRD_LOAD_ADDR;
|
|
initrd_size = load_image(initrd_filename,
|
|
phys_ram_base + initrd_base);
|
|
if (initrd_size < 0) {
|
|
cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
|
initrd_filename);
|
|
exit(1);
|
|
}
|
|
} else {
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
ppc_boot_device = 'm';
|
|
} else {
|
|
kernel_base = 0;
|
|
kernel_size = 0;
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
ppc_boot_device = '\0';
|
|
/* For now, OHW cannot boot from the network. */
|
|
for (i = 0; boot_device[i] != '\0'; i++) {
|
|
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
|
|
ppc_boot_device = boot_device[i];
|
|
break;
|
|
}
|
|
}
|
|
if (ppc_boot_device == '\0') {
|
|
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
isa_mem_base = 0xc0000000;
|
|
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
|
cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
|
|
exit(1);
|
|
}
|
|
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
|
|
pci_bus = pci_prep_init(i8259);
|
|
// pci_bus = i440fx_init();
|
|
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
|
PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
|
PPC_prep_io_write, sysctrl);
|
|
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
|
|
|
|
/* init basic PC hardware */
|
|
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
|
|
vga_ram_size, 0, 0);
|
|
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
|
// pit = pit_init(0x40, i8259[0]);
|
|
rtc_init(0x70, i8259[8]);
|
|
|
|
serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
|
|
nb_nics1 = nb_nics;
|
|
if (nb_nics1 > NE2000_NB_MAX)
|
|
nb_nics1 = NE2000_NB_MAX;
|
|
for(i = 0; i < nb_nics1; i++) {
|
|
if (nd_table[i].model == NULL
|
|
|| strcmp(nd_table[i].model, "ne2k_isa") == 0) {
|
|
isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
|
|
} else {
|
|
pci_nic_init(pci_bus, &nd_table[i], -1);
|
|
}
|
|
}
|
|
|
|
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
|
fprintf(stderr, "qemu: too many IDE bus\n");
|
|
exit(1);
|
|
}
|
|
|
|
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
|
|
index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
|
|
if (index != -1)
|
|
hd[i] = drives_table[index].bdrv;
|
|
else
|
|
hd[i] = NULL;
|
|
}
|
|
|
|
for(i = 0; i < MAX_IDE_BUS; i++) {
|
|
isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
|
|
hd[2 * i],
|
|
hd[2 * i + 1]);
|
|
}
|
|
i8042_init(i8259[1], i8259[12], 0x60);
|
|
DMA_init(1);
|
|
// AUD_init();
|
|
// SB16_init();
|
|
|
|
for(i = 0; i < MAX_FD; i++) {
|
|
index = drive_get_index(IF_FLOPPY, 0, i);
|
|
if (index != -1)
|
|
fd[i] = drives_table[index].bdrv;
|
|
else
|
|
fd[i] = NULL;
|
|
}
|
|
fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
|
|
|
|
/* Register speaker port */
|
|
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
|
|
register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
|
|
/* Register fake IO ports for PREP */
|
|
sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
|
|
register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
|
|
register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
|
|
/* System control ports */
|
|
register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
|
|
register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
|
|
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
|
|
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
|
|
/* PCI intack location */
|
|
PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
|
PPC_intack_write, NULL);
|
|
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
|
|
/* PowerPC control and status register group */
|
|
#if 0
|
|
PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
|
|
NULL);
|
|
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
|
#endif
|
|
|
|
if (usb_enabled) {
|
|
usb_ohci_init_pci(pci_bus, 3, -1);
|
|
}
|
|
|
|
m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
|
|
if (m48t59 == NULL)
|
|
return;
|
|
sysctrl->nvram = m48t59;
|
|
|
|
/* Initialise NVRAM */
|
|
nvram.opaque = m48t59;
|
|
nvram.read_fn = &m48t59_read;
|
|
nvram.write_fn = &m48t59_write;
|
|
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
|
kernel_base, kernel_size,
|
|
kernel_cmdline,
|
|
initrd_base, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
|
|
/* Special port to get debug messages from Open-Firmware */
|
|
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
|
|
}
|
|
|
|
QEMUMachine prep_machine = {
|
|
.name = "prep",
|
|
.desc = "PowerPC PREP platform",
|
|
.init = ppc_prep_init,
|
|
.ram_require = BIOS_SIZE + VGA_RAM_SIZE,
|
|
.max_cpus = 1,
|
|
};
|