e9b2bfaa64
Now that 32-bit KVM host support is gone, KVM can never be enabled unless CONFIG_AARCH64 is true, and some code paths are no longer reachable and can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200904154156.31943-3-peter.maydell@linaro.org
181 lines
7.8 KiB
C
181 lines
7.8 KiB
C
/*
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* KVM ARM ABI constant definitions
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*
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* Copyright (c) 2013 Linaro Limited
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*
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* Provide versions of KVM constant defines that can be used even
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* when CONFIG_KVM is not set and we don't have access to the
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* KVM headers. If CONFIG_KVM is set, we do a compile-time check
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* that we haven't got out of sync somehow.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef ARM_KVM_CONSTS_H
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#define ARM_KVM_CONSTS_H
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#ifdef CONFIG_KVM
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#include <linux/kvm.h>
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#include <linux/psci.h>
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#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
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#else
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#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
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#endif
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#define CP_REG_SIZE_SHIFT 52
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#define CP_REG_SIZE_MASK 0x00f0000000000000ULL
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#define CP_REG_SIZE_U32 0x0020000000000000ULL
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#define CP_REG_SIZE_U64 0x0030000000000000ULL
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#define CP_REG_ARM 0x4000000000000000ULL
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#define CP_REG_ARCH_MASK 0xff00000000000000ULL
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MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT);
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MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK);
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MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32);
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MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64);
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MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM);
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MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK);
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#define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
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#define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n))
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#define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
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#define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1)
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#define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2)
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#define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3)
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MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND);
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MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF);
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MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON);
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MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);
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#define QEMU_PSCI_0_2_FN_BASE 0x84000000
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#define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n))
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#define QEMU_PSCI_0_2_64BIT 0x40000000
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#define QEMU_PSCI_0_2_FN64_BASE \
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(QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT)
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#define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n))
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#define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0)
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#define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1)
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#define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2)
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#define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3)
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#define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4)
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#define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5)
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#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6)
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#define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7)
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#define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8)
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#define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9)
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#define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1)
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#define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2)
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#define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3)
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#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
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#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
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MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);
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/* PSCI v0.2 return values used by TCG emulation of PSCI */
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/* No Trusted OS migration to worry about when offlining CPUs */
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#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2
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/* We implement version 0.2 only */
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#define QEMU_PSCI_0_2_RET_VERSION_0_2 2
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MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
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MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
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(PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));
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/* PSCI return values (inclusive of all PSCI versions) */
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#define QEMU_PSCI_RET_SUCCESS 0
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#define QEMU_PSCI_RET_NOT_SUPPORTED -1
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#define QEMU_PSCI_RET_INVALID_PARAMS -2
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#define QEMU_PSCI_RET_DENIED -3
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#define QEMU_PSCI_RET_ALREADY_ON -4
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#define QEMU_PSCI_RET_ON_PENDING -5
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#define QEMU_PSCI_RET_INTERNAL_FAILURE -6
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#define QEMU_PSCI_RET_NOT_PRESENT -7
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#define QEMU_PSCI_RET_DISABLED -8
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MISMATCH_CHECK(QEMU_PSCI_RET_SUCCESS, PSCI_RET_SUCCESS);
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MISMATCH_CHECK(QEMU_PSCI_RET_NOT_SUPPORTED, PSCI_RET_NOT_SUPPORTED);
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MISMATCH_CHECK(QEMU_PSCI_RET_INVALID_PARAMS, PSCI_RET_INVALID_PARAMS);
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MISMATCH_CHECK(QEMU_PSCI_RET_DENIED, PSCI_RET_DENIED);
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MISMATCH_CHECK(QEMU_PSCI_RET_ALREADY_ON, PSCI_RET_ALREADY_ON);
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MISMATCH_CHECK(QEMU_PSCI_RET_ON_PENDING, PSCI_RET_ON_PENDING);
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MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE);
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MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT);
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MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
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/* Note that KVM uses overlapping values for AArch32 and AArch64
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* target CPU numbers. AArch32 targets:
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*/
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#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
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#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1
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/* AArch64 targets: */
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#define QEMU_KVM_ARM_TARGET_AEM_V8 0
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#define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
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#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
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#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
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#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
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/* There's no kernel define for this: sentinel value which
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* matches no KVM target value for either 64 or 32 bit
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*/
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#define QEMU_KVM_ARM_TARGET_NONE UINT_MAX
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
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#define CP_REG_ARM64 0x6000000000000000ULL
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#define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define CP_REG_ARM_COPROC_SHIFT 16
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#define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT)
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#define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
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#define CP_REG_ARM64_SYSREG_OP0_SHIFT 14
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#define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
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#define CP_REG_ARM64_SYSREG_OP1_SHIFT 11
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#define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
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#define CP_REG_ARM64_SYSREG_CRN_SHIFT 7
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#define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
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#define CP_REG_ARM64_SYSREG_CRM_SHIFT 3
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#define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define CP_REG_ARM64_SYSREG_OP2_SHIFT 0
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/* No kernel define but it's useful to QEMU */
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#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
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MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
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MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
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MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK);
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MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
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#undef MISMATCH_CHECK
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#endif
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