492c30af25
The current DMA routines are driven by a call in main_loop_wait() after every select. This patch converts the DMA code to be driven by a constantly rescheduled bottom half. The advantage of using a scheduled bottom half is that we can stop scheduling the bottom half when there no DMA channels are runnable. This means we can potentially detect this case and sleep longer in the main loop. The only two architectures implementing DMA_run() are cris and i386. For cris, I converted it to a simple repeating bottom half. I've only compile tested this as cris does not seem to work on a 64-bit host. It should be functionally identical to the previous implementation so I expect it to work. For x86, I've made sure to only fire the DMA bottom half if there is a DMA channel that is runnable. The effect of this is that unless you're using sb16 or a floppy disk, the DMA bottom half never fires. You probably should test this malc. My own benchmarks actually show slight improvement by it's possible the change in timing could affect your demos. Since v1, I've changed the code to use a BH instead of a timer. cris at least seems to depend on faster than 10ms polling. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5573 c046a42c-6fe2-441c-8c8c-71466251a162
92 lines
2.2 KiB
C
92 lines
2.2 KiB
C
/*
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* Arnewsh 5206 ColdFire system emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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#include "hw.h"
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#include "mcf.h"
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#include "sysemu.h"
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#include "boards.h"
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#define KERNEL_LOAD_ADDR 0x10000
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#define AN5206_MBAR_ADDR 0x10000000
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#define AN5206_RAMBAR_ADDR 0x20000000
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/* Stub functions for hardware that doesn't exist. */
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void pic_info(void)
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{
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}
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void irq_info(void)
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{
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}
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/* Board init. */
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static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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int kernel_size;
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uint64_t elf_entry;
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target_ulong entry;
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if (!cpu_model)
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cpu_model = "m5206";
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env = cpu_init(cpu_model);
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if (!env) {
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cpu_abort(env, "Unable to find m68k CPU definition\n");
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}
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/* Initialize CPU registers. */
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env->vbr = 0;
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/* TODO: allow changing MBAR and RAMBAR. */
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env->mbar = AN5206_MBAR_ADDR | 1;
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env->rambar0 = AN5206_RAMBAR_ADDR | 1;
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/* DRAM at address zero */
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cpu_register_physical_memory(0, ram_size,
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qemu_ram_alloc(ram_size) | IO_MEM_RAM);
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/* Internal SRAM. */
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cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
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qemu_ram_alloc(512) | IO_MEM_RAM);
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mcf5206_init(AN5206_MBAR_ADDR, env);
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/* Load kernel. */
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if (!kernel_filename) {
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fprintf(stderr, "Kernel image must be specified\n");
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exit(1);
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}
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kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
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entry = elf_entry;
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if (kernel_size < 0) {
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kernel_size = load_uboot(kernel_filename, &entry, NULL);
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}
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if (kernel_size < 0) {
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kernel_size = load_image(kernel_filename,
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phys_ram_base + KERNEL_LOAD_ADDR);
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entry = KERNEL_LOAD_ADDR;
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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exit(1);
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}
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env->pc = entry;
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}
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QEMUMachine an5206_machine = {
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.name = "an5206",
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.desc = "Arnewsh 5206",
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.init = an5206_init,
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.ram_require = 512,
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};
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