158 lines
4.6 KiB
C
158 lines
4.6 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_HOST_SPAPR_H
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#define PCI_HOST_SPAPR_H
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#include "hw/ppc/spapr.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/xics.h"
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_DMA_MAX_WINDOWS 2
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typedef struct sPAPRPHBState sPAPRPHBState;
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typedef struct spapr_pci_msi {
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uint32_t first_irq;
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uint32_t num;
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} spapr_pci_msi;
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typedef struct spapr_pci_msi_mig {
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uint32_t key;
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spapr_pci_msi value;
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} spapr_pci_msi_mig;
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struct sPAPRPHBState {
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PCIHostState parent_obj;
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uint32_t index;
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uint64_t buid;
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char *dtbusname;
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bool dr_enabled;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
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uint64_t mem64_win_pciaddr;
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hwaddr io_win_addr, io_win_size;
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MemoryRegion mem32window, mem64window, iowindow, msiwindow;
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uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
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hwaddr dma_win_addr, dma_win_size;
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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struct spapr_pci_lsi {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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spapr_pci_msi_mig *msi_devs;
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QLIST_ENTRY(sPAPRPHBState) list;
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bool ddw_enabled;
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uint64_t page_size_mask;
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uint64_t dma64_win_addr;
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uint32_t numa_node;
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};
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_MEM32_WIN_SIZE \
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((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */
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/* Without manual configuration, all PCI outbound windows will be
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* within this range */
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#define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */
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#define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */
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#define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
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}
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PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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void spapr_pci_rtas_init(void);
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sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
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PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
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uint32_t config_addr);
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/* VFIO EEH hooks */
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#ifdef CONFIG_LINUX
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bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
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int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
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unsigned int addr, int option);
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int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
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int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
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int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
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void spapr_phb_vfio_reset(DeviceState *qdev);
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#else
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static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
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{
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return false;
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}
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static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
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unsigned int addr, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
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int *state)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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}
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#endif
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void spapr_phb_dma_reset(sPAPRPHBState *sphb);
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#endif /* PCI_HOST_SPAPR_H */
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