Philippe Mathieu-Daudé 4cdd0a774d hw: Use QEMU_IS_ALIGNED() on parallel flash block size ... Use the QEMU_IS_ALIGNED() macro to verify the flash block size is properly aligned. It is quicker to process when reviewing. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200511205246.24621-1-philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>		2020-05-18 19:05:25 +02:00
..
boot.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00
Kconfig	riscv: virt: Use Goldfish RTC device	2020-02-10 12:01:38 -08:00
Makefile.objs
riscv_hart.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_e_prci.c
sifive_e.c	riscv: sifive_e: Support changing CPU type	2020-04-29 13:16:37 -07:00
sifive_gpio.c
sifive_plic.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_test.c
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c
sifive_u.c	qom: Drop parameter @errp of object_property_add() & friends	2020-05-15 07:07:58 +02:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	hw/riscv/spike: Allow more than one CPUs	2020-04-29 13:16:38 -07:00
trace-events
virt.c	hw: Use QEMU_IS_ALIGNED() on parallel flash block size	2020-05-18 19:05:25 +02:00