qemu-e2k/include
Suraj Jitindar Singh 5d62725b2f target/ppc: Implement the VTB for HV access
The virtual timebase register (VTB) is a 64-bit register which
increments at the same rate as the timebase register, present on POWER8
and later processors.

The register is able to be read/written by the hypervisor and read by
the supervisor. All other accesses are illegal.

Currently the VTB is just an alias for the timebase (TB) register.

Implement the VTB so that is can be read/written independent of the TB.
Make use of the existing method for accessing timebase facilities where
by the compensation is stored and used to compute the value on reads/is
updated on writes.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17 10:39:48 +11:00
..
authz
block nbd: Don't send oversize strings 2019-11-18 16:01:34 -06:00
chardev
crypto
disas
exec Memory: Enable writeback for given memory region 2019-12-16 10:46:35 +00:00
fpu
hw target/ppc: Implement the VTB for HV access 2019-12-17 10:39:48 +11:00
io
libdecnumber
migration migration: add new migration state wait-unplug 2019-10-29 18:55:26 -04:00
monitor
net
qapi
qemu Memory: Enable writeback for given memory region 2019-12-16 10:46:35 +00:00
qom
scsi
standard-headers linux-headers: Update 2019-12-17 10:39:48 +11:00
sysemu kvm: Introduce KVM irqchip change notifier 2019-11-26 10:11:30 +11:00
ui
user
elf.h
glib-compat.h
qemu-common.h
qemu-io.h
trace-tcg.h