qemu-e2k/target
Joseph Myers 5eebc49d2d target/i386: reimplement fyl2xp1 using floatx80 operations
The x87 fyl2xp1 emulation is currently based around conversion to
double.  This is inherently unsuitable for a good emulation of any
floatx80 operation, even before considering that it is a particularly
naive implementation using double (adding 1 then using log rather than
attempting a better emulation using log1p).

Reimplement using the soft-float operations, as was done for f2xm1; as
in that case, m68k has related operations but not exactly this one and
it seemed safest to implement directly rather than reusing the m68k
code to avoid accumulation of errors.

A test is included with many randomly generated inputs.  The
assumption of the test is that the result in round-to-nearest mode
should always be one of the two closest floating-point numbers to the
mathematical value of y * log2(x + 1); the implementation aims to do
somewhat better than that (about 70 correct bits before rounding).  I
haven't investigated how accurate hardware is.

Intel manuals describe a narrower range of valid arguments to this
instruction than AMD manuals.  The implementation accepts the wider
range (it's needed anyway for the core code to be reusable in a
subsequent patch reimplementing fyl2x), but the test only has inputs
in the narrower range so that it's valid on hardware that may reject
or produce poor results for inputs outside that range.

Code in the previous implementation that sets C2 for some out-of-range
arguments is not carried forward to the new implementation; C2 is
undefined for this instruction and I suspect that code was just
cut-and-pasted from the trigonometric instructions (fcos, fptan, fsin,
fsincos) where C2 *is* defined to be set for out-of-range arguments.

Signed-off-by: Joseph Myers <joseph@codesourcery.com>

Message-Id: <alpine.DEB.2.21.2006172320190.20587@digraph.polyomino.org.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-06-26 09:39:38 -04:00
..
alpha accel/tcg: Relax va restrictions on 64-bit guests 2020-05-15 15:25:16 +01:00
arm target/arm: Check supported KVM features globally (not per vCPU) 2020-06-23 11:39:47 +01:00
cris
hppa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
i386 target/i386: reimplement fyl2xp1 using floatx80 operations 2020-06-26 09:39:38 -04:00
lm32
m68k softfloat: merge floatx80_mod and floatx80_rem 2020-06-26 09:39:37 -04:00
microblaze target/microblaze: monitor: Increase the number of registers reported 2020-05-14 16:01:02 +02:00
mips target/mips: msa: Split helpers for MULV.<B|H|W|D> 2020-06-15 20:51:04 +02:00
moxie
nios2
openrisc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
ppc target/ppc: Restrict PPCVirtualHypervisorClass to system-mode 2020-06-12 11:12:45 -04:00
riscv hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 2020-06-19 08:25:27 -07:00
rx
s390x vfio-ccw: Add support for the schib region 2020-06-18 12:13:54 +02:00
sh4
sparc target/sparc/int32_helper: Extract and use excp_name_str() 2020-06-09 09:21:10 +02:00
tilegx
tricore target/tricore: Implement gdbstub 2020-06-01 16:55:13 +02:00
unicore32 target/unicore32: Prefer qemu_semihosting_log_out() over curses 2020-06-09 19:58:53 +02:00
xtensa target/xtensa fixes for 5.1: 2020-06-25 21:20:45 +01:00