Richard Henderson f251c01a62 target/riscv: Remove helper_set_rod_rounding_mode ... The only setting of RISCV_FRM_ROD is from the vector unit, and now handled by helper_set_rounding_mode_chkfrm. This helper is now unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-20 10:14:14 +10:00
..
insn_trans	target/riscv: Introduce helper_set_rounding_mode_chkfrm	2023-01-20 10:14:14 +10:00
arch_dump.c	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
cpu_helper.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
cpu_user.h
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Use TARGET_FMT_lx for env->mhartid	2023-01-20 10:14:13 +10:00
cpu.h	target/riscv/cpu: set cpu->cfg in register_cpu_props()	2023-01-20 10:14:13 +10:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1	2023-01-20 10:14:14 +10:00
debug.c	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
debug.h	target/riscv: Add itrigger support when icount is enabled	2023-01-06 10:42:55 +10:00
fpu_helper.c	target/riscv: Remove helper_set_rod_rounding_mode	2023-01-20 10:14:14 +10:00
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: Remove helper_set_rod_rounding_mode	2023-01-20 10:14:14 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c	kvm: allow target-specific accelerator properties	2022-10-10 09:23:16 +02:00
m128_helper.c
machine.c	hw/char: riscv_htif: Move registers from CPUArchState to HTIFState	2023-01-20 10:14:13 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
op_helper.c	target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+	2023-01-06 10:42:55 +10:00
pmp.c	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmp.h	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c	target/riscv: Remove helper_set_rod_rounding_mode	2023-01-20 10:14:14 +10:00
vector_helper.c	cleanup: Tweak and re-run return_directly.cocci	2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode