577 lines
15 KiB
C
577 lines
15 KiB
C
#ifndef E2K_TRANSLATE_H
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#define E2K_TRANSLATE_H
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#include "tcg/tcg-op.h"
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#include "exec/translator.h"
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#define IS_BASED(i) (((i) & 0x80) == 0)
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#define IS_REGULAR(i) (((i) & 0xc0) == 0x80)
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#define IS_IMM5(i) (((i) & 0xe0) == 0xc0)
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#define IS_IMM4(i) (((i) & 0xf0) == 0xc0)
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#define IS_LIT(i) (((i) & 0xf0) == 0xd0)
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#define IS_LIT16_LO(i) (((i) & 0x0e) == 0x00)
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#define IS_LIT16_HI(i) (((i) & 0x0e) == 0x04)
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#define IS_LIT32(i) (((i) & 0x0c) == 0x08)
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#define IS_LIT64(i) (((i) & 0x0c) == 0x0c)
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#define IS_GLOBAL(i) (((i) & 0xe0) == 0xe0)
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#define GET_BASED(i) ((i) & 0x7f)
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#define GET_REGULAR(i) ((i) & 0x3f)
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#define GET_IMM5(i) ((i) & 0x1f)
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#define GET_IMM4(i) ((i) & 0x0f)
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#define GET_LIT(i) ((i) & 0x03)
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#define GET_GLOBAL(i) ((i) & 0x1f)
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typedef enum {
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ALES_NONE = 0x00,
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ALES_PRESENT = 0x01,
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ALES_ALLOCATED = 0x02,
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} AlesFlag;
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typedef struct {
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TCGv_i32 cdi[32];
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TCGv_i64 pib[32];
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} CPUE2KAauPrefStateTCG;
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typedef struct CPUE2KStateTCG {
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TCGv pc;
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TCGv npc;
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TCGv_i64 ctprs[3];
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TCGv_i32 ct_cond;
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TCGv_i32 is_bp; /* breakpoint flag */
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TCGv_i32 wdbl;
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TCGv_i64 lsr;
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TCGv_i32 wd_base; /* holds wbs * 2 */
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TCGv_i32 wd_size; /* holds wsz * 2 */
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TCGv_i32 boff; /* holds rbs * 2 */
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TCGv_i32 bsize; /* holds rsz * 2 + 2 */
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TCGv_i32 bcur; /* holds rcur * 2 */
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TCGv_i64 pregs;
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TCGv_i32 psize; /* holds psz */
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TCGv_i32 pcur; /* holds pcur */
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/* AAU */
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TCGv_i32 aasti[16];
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TCGv_i32 aasti_tags;
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TCGv_i32 aaind[16];
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TCGv_i32 aaind_tags;
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TCGv_i32 aaincr[8];
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TCGv_i32 aaincr_tags;
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TCGv_i64 aad_lo[32];
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TCGv_i64 aad_hi[32];
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CPUE2KAauPrefStateTCG aapl, aapr;
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} CPUE2KStateTCG;
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extern struct CPUE2KStateTCG e2k_cs;
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typedef struct UnpackedBundle {
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uint32_t hs;
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uint32_t ss;
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uint32_t als[6];
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uint32_t cs0;
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uint16_t ales[6];
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uint32_t cs1;
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uint16_t aas[6];
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uint32_t lts[4];
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uint32_t pls[3];
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uint32_t cds[3];
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bool ss_present;
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bool als_present[6];
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bool cs0_present;
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AlesFlag ales_present[6];
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bool cs1_present;
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bool aas_present[6];
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bool lts_present[4];
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bool pls_present[3];
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bool cds_present[3];
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} UnpackedBundle;
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typedef enum {
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AL_RESULT_NONE = 0,
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AL_RESULT_SIZE_MASK = 0x3,
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AL_RESULT_32 = 0x00,
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AL_RESULT_64 = 0x01,
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AL_RESULT_80 = 0x02,
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AL_RESULT_128 = 0x03,
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AL_RESULT_TYPE_MASK = 0xc,
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AL_RESULT_REG = 0x04,
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AL_RESULT_PREG = 0x08,
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AL_RESULT_CTPR = 0x0c,
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AL_RESULT_REG32 = AL_RESULT_REG | AL_RESULT_32,
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AL_RESULT_REG64 = AL_RESULT_REG | AL_RESULT_64,
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AL_RESULT_REG80 = AL_RESULT_REG | AL_RESULT_80,
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AL_RESULT_REG128 = AL_RESULT_REG | AL_RESULT_128,
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AL_RESULT_CTPR32 = AL_RESULT_CTPR | AL_RESULT_32,
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AL_RESULT_CTPR64 = AL_RESULT_CTPR | AL_RESULT_64,
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} AlResultType;
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#define e2k_al_result_size(x) ((x) & AL_RESULT_SIZE_MASK)
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#define e2k_al_result_type(x) ((x) & AL_RESULT_TYPE_MASK)
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typedef struct {
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AlResultType type;
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/* check tag for 32-bit ops if wdbl is set */
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bool check_tag;
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/* poison result if tag is not zero */
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bool poison;
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union {
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struct {
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uint8_t dst; /* %rN, 1st phase */
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TCGv_i32 index;
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TCGv_i32 tag;
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union {
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TCGv_i32 v32;
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TCGv_i64 v64;
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};
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union {
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TCGv_i32 x32; /* FX ops */
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TCGv_i64 x64; /* SIMD ops v5+ */
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};
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} reg;
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struct {
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int index;
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union {
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TCGv_i32 v32;
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TCGv_i64 v64;
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};
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} ctpr;
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struct {
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int index;
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TCGv_i32 val;
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} preg;
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};
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} AlResult;
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typedef enum {
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AAU_RESULT_NONE,
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AAU_RESULT_REG32,
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AAU_RESULT_REG64,
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} AauResultType;
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typedef struct {
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AauResultType type;
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uint8_t dst;
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TCGv_i32 index;
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union {
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TCGv_i32 v32;
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TCGv_i64 v64;
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};
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} AauResult;
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typedef struct {
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int reg; // -1 means do not write
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TCGv_i32 value;
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} PlResult;
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typedef enum {
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CT_NONE,
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CT_IBRANCH,
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CT_JUMP,
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CT_CALL,
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} ControlTransferType;
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typedef struct {
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ControlTransferType type;
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union {
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target_ulong target;
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TCGv_i64 ctpr;
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} u;
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int wbs;
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bool is_branch;
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} ControlTransfer;
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typedef struct DisasContext {
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DisasContextBase base;
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UnpackedBundle bundle;
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target_ulong pc;
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int jump_ctpr;
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int mmuidx;
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uint8_t mas[6];
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bool loop_mode;
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TCGv_i32 is_prologue;
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TCGv_i32 is_epilogue;
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/* optional, can be NULL */
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TCGv_i32 mlock;
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int version;
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/* Force ILLOP for bad instruction format for cases where real CPU
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do not generate it. */
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bool strict;
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// Temporary values.
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TCGv_i32 t32[64];
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TCGv_i64 t64[32];
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TCGv ttl[8];
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// Allocated temporary values count.
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int t32_len;
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int t64_len;
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int ttl_len;
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/* illegal tag for delayed exception */
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TCGv_i32 illtag;
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TCGv_i64 cond[6];
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AlResult al_results[6];
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TCGv_i32 al_cond[6];
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AauResult aau_results[4];
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int aau_am[4];
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PlResult pl_results[3];
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ControlTransfer ct;
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} DisasContext;
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/* exception generated in translation time */
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void e2k_tr_gen_exception(DisasContext *dc, int which);
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void e2k_tr_gen_exception_no_spill(DisasContext *ctx, int excp);
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/* exception generated in runtime */
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static inline void e2k_gen_exception(int excp)
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{
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TCGv_i32 t0 = tcg_const_i32(excp);
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// TODO: check if need to save state
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gen_helper_raise_exception(cpu_env, t0);
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tcg_temp_free_i32(t0);
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}
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#define e2k_todo(ctx, fmt, ...) \
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do { \
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if (unlikely(qemu_loglevel_mask(LOG_UNIMP))) { \
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qemu_log("%#lx: todo: ", ctx->pc); \
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qemu_log(fmt, ## __VA_ARGS__); \
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qemu_log("\n"); \
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} \
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} while (0)
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#define e2k_todo_illop(ctx, fmt, ...) \
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do { \
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e2k_todo(ctx, fmt, ## __VA_ARGS__); \
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e2k_tr_gen_exception(ctx, E2K_EXCP_ILLOPC); \
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} while (0)
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static inline void e2k_gen_mask_i64(TCGv_i64 ret, TCGv_i64 len)
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{
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TCGv_i64 one = tcg_const_i64(1);
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_shl_i64(t0, one, len);
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tcg_gen_subi_i64(ret, t0, 1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(one);
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}
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static inline void e2k_gen_maski_i64(TCGv_i64 ret, int len)
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{
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TCGv_i64 t0 = tcg_const_i64(len);
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e2k_gen_mask_i64(ret, t0);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg1,
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TCGv_i64 offset, TCGv_i64 len)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_shr_i64(t0, arg1, offset);
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e2k_gen_mask_i64(t1, len);
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tcg_gen_and_i64(ret, t0, t1);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
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TCGv_i64 arg2, TCGv_i64 offset, TCGv_i64 len)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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TCGv_i64 t3 = tcg_temp_new_i64();
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TCGv_i64 t4 = tcg_temp_new_i64();
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TCGv_i64 t5 = tcg_temp_new_i64();
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e2k_gen_mask_i64(t0, len);
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tcg_gen_shl_i64(t1, t0, offset);
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tcg_gen_not_i64(t2, t1);
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tcg_gen_and_i64(t3, arg1, t2);
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tcg_gen_and_i64(t4, arg2, t0);
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tcg_gen_shl_i64(t5, t4, offset);
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tcg_gen_or_i64(ret, t3, t5);
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tcg_temp_free_i64(t5);
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tcg_temp_free_i64(t4);
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tcg_temp_free_i64(t3);
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tcg_temp_free_i64(t2);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t0);
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}
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static inline TCGv_i32 e2k_get_temp_i32(DisasContext *dc)
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{
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assert(dc->t32_len < ARRAY_SIZE(dc->t32));
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return dc->t32[dc->t32_len++] = tcg_temp_local_new_i32();
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}
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static inline TCGv_i32 e2k_get_const_i32(DisasContext *dc, uint32_t value)
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{
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assert(dc->t32_len < ARRAY_SIZE(dc->t32));
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return dc->t32[dc->t32_len++] = tcg_const_local_i32(value);
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}
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static inline TCGv_i64 e2k_get_temp_i64(DisasContext *dc)
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{
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assert(dc->t64_len < ARRAY_SIZE(dc->t64));
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return dc->t64[dc->t64_len++] = tcg_temp_local_new_i64();
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}
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static inline TCGv_i64 e2k_get_const_i64(DisasContext *dc, uint64_t value)
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{
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assert(dc->t64_len < ARRAY_SIZE(dc->t64));
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return dc->t64[dc->t64_len++] = tcg_const_local_i64(value);
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}
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static inline TCGv e2k_get_temp(DisasContext *dc)
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{
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assert(dc->ttl_len < ARRAY_SIZE(dc->ttl));
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return dc->ttl[dc->ttl_len++] = tcg_temp_local_new();
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}
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static inline void e2k_gen_save_pc(target_ulong pc)
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{
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tcg_gen_movi_tl(e2k_cs.pc, pc);
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}
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static inline void e2k_gen_save_cpu_state(DisasContext *ctx)
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{
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e2k_gen_save_pc(ctx->pc);
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}
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static inline void e2k_gen_lcnt_i64(TCGv_i64 ret)
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{
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tcg_gen_andi_i64(ret, e2k_cs.lsr, (1UL << 32) - 1);
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}
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static inline void e2k_gen_lcnt_i32(TCGv_i32 ret)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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e2k_gen_lcnt_i64(t0);
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tcg_gen_extrl_i64_i32(ret, t0);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_lcnt_set_i32(TCGv_i32 value)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t0, value);
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tcg_gen_deposit_i64(e2k_cs.lsr, e2k_cs.lsr, t0, LSR_LCNT_OFF, LSR_LCNT_LEN);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_ecnt_i64(TCGv_i64 ret)
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{
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tcg_gen_extract_i64(ret, e2k_cs.lsr, LSR_ECNT_OFF, LSR_ECNT_LEN);
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}
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static inline void e2k_gen_ecnt_i32(TCGv_i32 ret)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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e2k_gen_ecnt_i64(t0);
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tcg_gen_extrl_i64_i32(ret, t0);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_ecnt_set_i32(TCGv_i32 value)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t0, value);
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tcg_gen_deposit_i64(e2k_cs.lsr, e2k_cs.lsr, t0, LSR_ECNT_OFF, LSR_ECNT_LEN);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_pcnt_i32(TCGv_i32 ret)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extract_i64(t0, e2k_cs.lsr, LSR_PCNT_OFF, LSR_PCNT_LEN);
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tcg_gen_extrl_i64_i32(ret, t0);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_pcnt_set_i32(TCGv_i32 value)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t0, value);
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tcg_gen_deposit_i64(e2k_cs.lsr, e2k_cs.lsr, t0, LSR_PCNT_OFF, LSR_PCNT_LEN);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_lsr_strem_i32(TCGv_i32 ret)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extract_i64(t0, e2k_cs.lsr, LSR_STRMD_OFF, LSR_STRMD_LEN);
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tcg_gen_extrl_i64_i32(ret, t0);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_lsr_strem_set_i32(TCGv_i32 value)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t0, value);
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tcg_gen_deposit_i64(e2k_cs.lsr, e2k_cs.lsr, t0, LSR_STRMD_OFF,
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LSR_STRMD_LEN);
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tcg_temp_free_i64(t0);
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}
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static inline void e2k_gen_lcntex(TCGv_i32 ret)
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t0, e2k_cs.lsr);
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tcg_gen_setcondi_i32(TCG_COND_EQ, ret, t0, 0);
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tcg_temp_free_i32(t0);
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}
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void e2k_gen_store_preg(int idx, TCGv_i32 val);
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void e2k_gen_reg_tag_read_i64(TCGv_i32 ret, TCGv_i32 idx);
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void e2k_gen_reg_tag_read_i32(TCGv_i32 ret, TCGv_i32 idx);
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void e2k_gen_reg_tag_write_i64(TCGv_i32 value, TCGv_i32 idx);
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void e2k_gen_reg_tag_write_i32(TCGv_i32 value, TCGv_i32 idx);
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static inline void e2k_gen_reg_tag_writei_i64(int value, TCGv_i32 idx)
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{
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TCGv_i32 t0 = tcg_const_i32(value);
|
|
e2k_gen_reg_tag_write_i64(t0, idx);
|
|
tcg_temp_free_i32(t0);
|
|
}
|
|
|
|
static inline void e2k_gen_reg_tag_writei_i32(int value, TCGv_i32 idx)
|
|
{
|
|
TCGv_i32 t0 = tcg_const_i32(value);
|
|
e2k_gen_reg_tag_write_i32(t0, idx);
|
|
tcg_temp_free_i32(t0);
|
|
}
|
|
|
|
static inline void e2k_gen_reg_tag_extract_lo(TCGv_i32 ret, TCGv_i32 tags)
|
|
{
|
|
tcg_gen_andi_i32(ret, tags, GEN_MASK(0, E2K_TAG_SIZE));
|
|
}
|
|
|
|
static inline void e2k_gen_reg_tag_extract_hi(TCGv_i32 ret, TCGv_i32 tags)
|
|
{
|
|
tcg_gen_shri_i32(ret, tags, E2K_TAG_SIZE);
|
|
}
|
|
|
|
void e2k_gen_reg_tag_check_i64(TCGv_i32 ret, TCGv_i32 tag);
|
|
void e2k_gen_reg_tag_check_i32(TCGv_i32 ret, TCGv_i32 tag);
|
|
|
|
void e2k_gen_reg_index_from_wregi(TCGv_i32 ret, int idx);
|
|
void e2k_gen_reg_index_from_bregi(TCGv_i32 ret, int idx);
|
|
void e2k_gen_reg_index_from_gregi(TCGv_i32 ret, int idx);
|
|
static inline void e2k_gen_reg_index(TCGv_i32 ret, uint8_t arg)
|
|
{
|
|
if (IS_BASED(arg)) {
|
|
e2k_gen_reg_index_from_bregi(ret, GET_BASED(arg));
|
|
} else if (IS_REGULAR(arg)) {
|
|
e2k_gen_reg_index_from_wregi(ret, GET_REGULAR(arg));
|
|
} else if (IS_GLOBAL(arg)) {
|
|
e2k_gen_reg_index_from_gregi(ret, GET_GLOBAL(arg));
|
|
} else {
|
|
e2k_gen_exception(E2K_EXCP_ILLOPN);
|
|
}
|
|
}
|
|
|
|
void e2k_gen_reg_read_i64(TCGv_i64 ret, TCGv_i32 idx);
|
|
void e2k_gen_reg_read_i32(TCGv_i32 ret, TCGv_i32 idx);
|
|
void e2k_gen_reg_write_i64(TCGv_i64 value, TCGv_i32 idx);
|
|
void e2k_gen_reg_write_i32(TCGv_i32 value, TCGv_i32 idx);
|
|
|
|
void e2k_gen_xreg_read_i64(TCGv_i64 ret, TCGv_i32 idx);
|
|
void e2k_gen_xreg_read_i32(TCGv_i32 ret, TCGv_i32 idx);
|
|
void e2k_gen_xreg_read16u_i32(TCGv_i32 ret, TCGv_i32 idx);
|
|
void e2k_gen_xreg_write_i64(TCGv_i64 value, TCGv_i32 idx);
|
|
void e2k_gen_xreg_write_i32(TCGv_i32 value, TCGv_i32 idx);
|
|
void e2k_gen_xreg_write16u_i32(TCGv_i32 value, TCGv_i32 idx);
|
|
|
|
void e2k_gen_preg_i64(TCGv_i64 ret, int reg);
|
|
void e2k_gen_preg_i32(TCGv_i32 ret, int reg);
|
|
TCGv_i64 e2k_get_preg(DisasContext *dc, int reg);
|
|
void e2k_gen_cond_i32(DisasContext *ctx, TCGv_i32 ret, uint8_t psrc);
|
|
|
|
static inline void e2k_gen_cond_i64(DisasContext *ctx, TCGv_i64 ret,
|
|
uint8_t psrc)
|
|
{
|
|
TCGv_i32 t0 = tcg_temp_new_i32();
|
|
|
|
e2k_gen_cond_i32(ctx, t0, psrc);
|
|
tcg_gen_extu_i32_i64(ret, t0);
|
|
|
|
tcg_temp_free_i32(t0);
|
|
}
|
|
|
|
static inline void e2k_gen_is_last_iter(TCGv_i32 ret)
|
|
{
|
|
TCGv_i32 t0 = tcg_temp_new_i32();
|
|
TCGv_i32 t1 = tcg_temp_new_i32();
|
|
TCGv_i64 t2 = tcg_temp_new_i64();
|
|
TCGv_i32 t3 = tcg_temp_new_i32();
|
|
|
|
e2k_gen_lcnt_i32(t0);
|
|
tcg_gen_setcondi_i32(TCG_COND_LTU, t1, t0, 2);
|
|
tcg_gen_andi_i64(t2, e2k_cs.lsr, LSR_VLC_BIT);
|
|
tcg_gen_setcondi_i64(TCG_COND_NE, t2, t2, 0);
|
|
tcg_gen_extrl_i64_i32(t3, t2);
|
|
tcg_gen_and_i32(ret, t1, t3);
|
|
|
|
tcg_temp_free_i32(t3);
|
|
tcg_temp_free_i64(t2);
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t0);
|
|
}
|
|
|
|
static inline void e2k_gen_is_loop_end_i32(TCGv_i32 ret)
|
|
{
|
|
TCGv_i32 t0 = tcg_temp_new_i32();
|
|
TCGv_i32 t1 = tcg_temp_new_i32();
|
|
TCGv_i32 t2 = tcg_temp_new_i32();
|
|
|
|
e2k_gen_ecnt_i32(t0);
|
|
tcg_gen_setcondi_i32(TCG_COND_EQ, t1, t0, 0);
|
|
e2k_gen_is_last_iter(t2);
|
|
tcg_gen_and_i32(ret, t1, t2);
|
|
|
|
tcg_temp_free_i32(t2);
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t0);
|
|
}
|
|
|
|
void e2k_decode_jmp(DisasContext *ctx);
|
|
void e2k_control_execute(DisasContext *ctx);
|
|
void e2k_control_window_change(DisasContext *ctx);
|
|
void e2k_stubs_commit(DisasContext *ctx);
|
|
|
|
void e2k_alc_init(DisasContext *ctx);
|
|
void e2k_alc_execute(DisasContext *ctx);
|
|
void e2k_alc_commit(DisasContext *ctx);
|
|
|
|
void e2k_aau_execute(DisasContext *ctx);
|
|
void e2k_aau_commit(DisasContext *ctx);
|
|
void e2k_plu_execute(DisasContext *ctx);
|
|
void e2k_plu_commit(DisasContext *ctx);
|
|
|
|
#endif
|