qemu-e2k/target-i386
Andre Przywara 31501a714b target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:10:36 +02:00
..
cpu.h target-i386: move recently added vmstate fields at the end of the structure 2009-10-05 22:41:04 +02:00
exec.h Work around OpenSolaris sys/regset.h namespace pollution 2009-09-12 12:36:11 +00:00
helper_template.h
helper.c x86: mce_banks always have the same size 2009-10-05 09:32:41 -05:00
helper.h target-i386: implement lzcnt emulation 2009-10-23 17:10:36 +02:00
kvm.c gcc wants 1st static and then const 2009-09-25 19:52:06 +00:00
machine.c x86: add 'static' to please Sparse 2009-10-18 14:51:10 +00:00
op_helper.c target-i386: implement lzcnt emulation 2009-10-23 17:10:36 +02:00
ops_sse_header.h target-i386: add SSE4a instruction support 2009-10-04 14:09:41 +02:00
ops_sse.h target-i386: add SSE4a instruction support 2009-10-04 14:09:41 +02:00
svm.h
TODO
translate.c target-i386: implement lzcnt emulation 2009-10-23 17:10:36 +02:00