909 lines
28 KiB
C
909 lines
28 KiB
C
/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "mc146818rtc.h"
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#ifdef TARGET_I386
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#include "apic.h"
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#endif
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//#define DEBUG_CMOS
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//#define DEBUG_COALESCED
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#ifdef DEBUG_CMOS
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# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define CMOS_DPRINTF(format, ...) do { } while (0)
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#endif
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#ifdef DEBUG_COALESCED
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# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define DPRINTF_C(format, ...) do { } while (0)
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#endif
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#define NSEC_PER_SEC 1000000000LL
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#define SEC_PER_MIN 60
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#define MIN_PER_HOUR 60
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#define SEC_PER_HOUR 3600
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#define HOUR_PER_DAY 24
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#define SEC_PER_DAY 86400
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#define RTC_REINJECT_ON_ACK_COUNT 20
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#define RTC_CLOCK_RATE 32768
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#define UIP_HOLD_LENGTH (8 * NSEC_PER_SEC / 32768)
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typedef struct RTCState {
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ISADevice dev;
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MemoryRegion io;
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uint8_t cmos_data[128];
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uint8_t cmos_index;
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int32_t base_year;
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uint64_t base_rtc;
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uint64_t last_update;
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int64_t offset;
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qemu_irq irq;
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qemu_irq sqw_irq;
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer;
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int64_t next_periodic_time;
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/* update-ended timer */
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QEMUTimer *update_timer;
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uint64_t next_alarm_time;
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uint16_t irq_reinject_on_ack_count;
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uint32_t irq_coalesced;
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uint32_t period;
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QEMUTimer *coalesced_timer;
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Notifier clock_reset_notifier;
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LostTickPolicy lost_tick_policy;
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Notifier suspend_notifier;
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} RTCState;
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static void rtc_set_time(RTCState *s);
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static void rtc_update_time(RTCState *s);
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static void rtc_set_cmos(RTCState *s, const struct tm *tm);
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static inline int rtc_from_bcd(RTCState *s, int a);
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static uint64_t get_next_alarm(RTCState *s);
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static inline bool rtc_running(RTCState *s)
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{
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return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
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(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
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}
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static uint64_t get_guest_rtc_ns(RTCState *s)
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{
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uint64_t guest_rtc;
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uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
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guest_rtc = s->base_rtc * NSEC_PER_SEC
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+ guest_clock - s->last_update + s->offset;
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return guest_rtc;
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}
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s)
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{
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if (s->irq_coalesced == 0) {
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qemu_del_timer(s->coalesced_timer);
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1;
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int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
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muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
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qemu_mod_timer(s->coalesced_timer, next_clock);
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}
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}
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static void rtc_coalesced_timer(void *opaque)
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{
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RTCState *s = opaque;
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if (s->irq_coalesced != 0) {
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apic_reset_irq_delivered();
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s->cmos_data[RTC_REG_C] |= 0xc0;
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DPRINTF_C("cmos: injecting from timer\n");
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qemu_irq_raise(s->irq);
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--;
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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s->irq_coalesced);
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}
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}
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rtc_coalesced_timer_update(s);
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}
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#endif
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/* handle periodic timer */
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static void periodic_timer_update(RTCState *s, int64_t current_time)
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0
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&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2)
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1);
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#ifdef TARGET_I386
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if (period != s->period) {
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s->irq_coalesced = (s->irq_coalesced * s->period) / period;
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DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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}
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s->period = period;
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time =
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muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer);
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}
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}
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static void rtc_periodic_timer(void *opaque)
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{
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RTCState *s = opaque;
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periodic_timer_update(s, s->next_periodic_time);
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s->cmos_data[RTC_REG_C] |= REG_C_PF;
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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#ifdef TARGET_I386
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if (s->lost_tick_policy == LOST_TICK_SLEW) {
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered();
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qemu_irq_raise(s->irq);
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++;
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rtc_coalesced_timer_update(s);
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DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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s->irq_coalesced);
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}
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} else
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#endif
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qemu_irq_raise(s->irq);
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}
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq);
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}
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}
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/* handle update-ended timer */
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static void check_update_timer(RTCState *s)
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{
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uint64_t next_update_time;
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uint64_t guest_nsec;
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int next_alarm_sec;
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/* From the data sheet: "Holding the dividers in reset prevents
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* interrupts from operating, while setting the SET bit allows"
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* them to occur. However, it will prevent an alarm interrupt
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* from occurring, because the time of day is not updated.
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*/
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if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
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qemu_del_timer(s->update_timer);
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return;
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}
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if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
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(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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qemu_del_timer(s->update_timer);
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return;
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}
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if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
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(s->cmos_data[RTC_REG_C] & REG_C_AF)) {
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qemu_del_timer(s->update_timer);
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return;
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}
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guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
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/* if UF is clear, reprogram to next second */
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next_update_time = qemu_get_clock_ns(rtc_clock)
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+ NSEC_PER_SEC - guest_nsec;
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/* Compute time of next alarm. One second is already accounted
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* for in next_update_time.
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*/
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next_alarm_sec = get_next_alarm(s);
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s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
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if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
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/* UF is set, but AF is clear. Program the timer to target
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* the alarm time. */
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next_update_time = s->next_alarm_time;
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}
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if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
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qemu_mod_timer(s->update_timer, next_update_time);
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}
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}
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static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
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{
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if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
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hour %= 12;
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if (s->cmos_data[RTC_HOURS] & 0x80) {
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hour += 12;
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}
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}
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return hour;
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}
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static uint64_t get_next_alarm(RTCState *s)
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{
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int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
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int32_t hour, min, sec;
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rtc_update_time(s);
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alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
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alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
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alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
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alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
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cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
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cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
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cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
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cur_hour = convert_hour(s, cur_hour);
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if (alarm_hour == -1) {
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alarm_hour = cur_hour;
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if (alarm_min == -1) {
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alarm_min = cur_min;
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if (alarm_sec == -1) {
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alarm_sec = cur_sec + 1;
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} else if (cur_sec > alarm_sec) {
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alarm_min++;
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}
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} else if (cur_min == alarm_min) {
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if (alarm_sec == -1) {
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alarm_sec = cur_sec + 1;
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} else {
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if (cur_sec > alarm_sec) {
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alarm_hour++;
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}
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}
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if (alarm_sec == SEC_PER_MIN) {
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/* wrap to next hour, minutes is not in don't care mode */
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alarm_sec = 0;
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alarm_hour++;
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}
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} else if (cur_min > alarm_min) {
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alarm_hour++;
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}
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} else if (cur_hour == alarm_hour) {
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if (alarm_min == -1) {
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alarm_min = cur_min;
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if (alarm_sec == -1) {
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alarm_sec = cur_sec + 1;
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} else if (cur_sec > alarm_sec) {
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alarm_min++;
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}
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if (alarm_sec == SEC_PER_MIN) {
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alarm_sec = 0;
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alarm_min++;
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}
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/* wrap to next day, hour is not in don't care mode */
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alarm_min %= MIN_PER_HOUR;
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} else if (cur_min == alarm_min) {
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if (alarm_sec == -1) {
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alarm_sec = cur_sec + 1;
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}
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/* wrap to next day, hours+minutes not in don't care mode */
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alarm_sec %= SEC_PER_MIN;
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}
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}
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/* values that are still don't care fire at the next min/sec */
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if (alarm_min == -1) {
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alarm_min = 0;
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}
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if (alarm_sec == -1) {
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alarm_sec = 0;
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}
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/* keep values in range */
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if (alarm_sec == SEC_PER_MIN) {
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alarm_sec = 0;
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alarm_min++;
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}
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if (alarm_min == MIN_PER_HOUR) {
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alarm_min = 0;
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alarm_hour++;
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}
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alarm_hour %= HOUR_PER_DAY;
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hour = alarm_hour - cur_hour;
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min = hour * MIN_PER_HOUR + alarm_min - cur_min;
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sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
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return sec <= 0 ? sec + SEC_PER_DAY : sec;
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}
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static void rtc_update_timer(void *opaque)
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{
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RTCState *s = opaque;
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int32_t irqs = REG_C_UF;
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int32_t new_irqs;
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assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
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/* UIP might have been latched, update time and clear it. */
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rtc_update_time(s);
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
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irqs |= REG_C_AF;
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
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}
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}
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new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
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s->cmos_data[RTC_REG_C] |= irqs;
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if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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qemu_irq_raise(s->irq);
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}
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check_update_timer(s);
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}
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static void cmos_ioport_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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s->cmos_index = data & 0x7f;
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} else {
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CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data);
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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s->cmos_data[s->cmos_index] = data;
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check_update_timer(s);
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break;
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case RTC_IBM_PS2_CENTURY_BYTE:
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s->cmos_index = RTC_CENTURY;
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/* fall through */
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case RTC_CENTURY:
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (rtc_running(s)) {
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rtc_set_time(s);
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check_update_timer(s);
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}
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break;
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case RTC_REG_A:
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if ((data & 0x60) == 0x60) {
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if (rtc_running(s)) {
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rtc_update_time(s);
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}
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/* What happens to UIP when divider reset is enabled is
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* unclear from the datasheet. Shouldn't matter much
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* though.
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*/
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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} else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
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(data & 0x70) <= 0x20) {
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/* when the divider reset is removed, the first update cycle
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* begins one-half second later*/
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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s->offset = 500000000;
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rtc_set_time(s);
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}
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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}
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
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check_update_timer(s);
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* update cmos to when the rtc was stopping */
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if (rtc_running(s)) {
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rtc_update_time(s);
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}
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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data &= ~REG_B_UIE;
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} else {
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/* if disabling set mode, update the time */
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if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
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(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
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s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
|
|
rtc_set_time(s);
|
|
}
|
|
}
|
|
/* if an interrupt flag is already set when the interrupt
|
|
* becomes enabled, raise an interrupt immediately. */
|
|
if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
|
|
s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
|
|
qemu_irq_raise(s->irq);
|
|
} else {
|
|
s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
|
|
qemu_irq_lower(s->irq);
|
|
}
|
|
s->cmos_data[RTC_REG_B] = data;
|
|
periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
|
|
check_update_timer(s);
|
|
break;
|
|
case RTC_REG_C:
|
|
case RTC_REG_D:
|
|
/* cannot write to them */
|
|
break;
|
|
default:
|
|
s->cmos_data[s->cmos_index] = data;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline int rtc_to_bcd(RTCState *s, int a)
|
|
{
|
|
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
|
return a;
|
|
} else {
|
|
return ((a / 10) << 4) | (a % 10);
|
|
}
|
|
}
|
|
|
|
static inline int rtc_from_bcd(RTCState *s, int a)
|
|
{
|
|
if ((a & 0xc0) == 0xc0) {
|
|
return -1;
|
|
}
|
|
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
|
return a;
|
|
} else {
|
|
return ((a >> 4) * 10) + (a & 0x0f);
|
|
}
|
|
}
|
|
|
|
static void rtc_get_time(RTCState *s, struct tm *tm)
|
|
{
|
|
tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
|
|
tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
|
|
tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
|
|
if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
|
|
tm->tm_hour %= 12;
|
|
if (s->cmos_data[RTC_HOURS] & 0x80) {
|
|
tm->tm_hour += 12;
|
|
}
|
|
}
|
|
tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
|
|
tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
|
|
tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
|
|
tm->tm_year =
|
|
rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
|
|
rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
|
|
}
|
|
|
|
static void rtc_set_time(RTCState *s)
|
|
{
|
|
struct tm tm;
|
|
|
|
rtc_get_time(s, &tm);
|
|
s->base_rtc = mktimegm(&tm);
|
|
s->last_update = qemu_get_clock_ns(rtc_clock);
|
|
|
|
rtc_change_mon_event(&tm);
|
|
}
|
|
|
|
static void rtc_set_cmos(RTCState *s, const struct tm *tm)
|
|
{
|
|
int year;
|
|
|
|
s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
|
|
s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
|
|
if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
|
|
/* 24 hour format */
|
|
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
|
|
} else {
|
|
/* 12 hour format */
|
|
int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
|
|
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
|
|
if (tm->tm_hour >= 12)
|
|
s->cmos_data[RTC_HOURS] |= 0x80;
|
|
}
|
|
s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
|
s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
|
|
s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
|
year = tm->tm_year + 1900 - s->base_year;
|
|
s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
|
|
s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
|
|
}
|
|
|
|
static void rtc_update_time(RTCState *s)
|
|
{
|
|
struct tm ret;
|
|
time_t guest_sec;
|
|
int64_t guest_nsec;
|
|
|
|
guest_nsec = get_guest_rtc_ns(s);
|
|
guest_sec = guest_nsec / NSEC_PER_SEC;
|
|
gmtime_r(&guest_sec, &ret);
|
|
rtc_set_cmos(s, &ret);
|
|
}
|
|
|
|
static int update_in_progress(RTCState *s)
|
|
{
|
|
int64_t guest_nsec;
|
|
|
|
if (!rtc_running(s)) {
|
|
return 0;
|
|
}
|
|
if (qemu_timer_pending(s->update_timer)) {
|
|
int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
|
|
/* Latch UIP until the timer expires. */
|
|
if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
|
|
s->cmos_data[RTC_REG_A] |= REG_A_UIP;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
guest_nsec = get_guest_rtc_ns(s);
|
|
/* UIP bit will be set at last 244us of every second. */
|
|
if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
RTCState *s = opaque;
|
|
int ret;
|
|
if ((addr & 1) == 0) {
|
|
return 0xff;
|
|
} else {
|
|
switch(s->cmos_index) {
|
|
case RTC_IBM_PS2_CENTURY_BYTE:
|
|
s->cmos_index = RTC_CENTURY;
|
|
/* fall through */
|
|
case RTC_CENTURY:
|
|
case RTC_SECONDS:
|
|
case RTC_MINUTES:
|
|
case RTC_HOURS:
|
|
case RTC_DAY_OF_WEEK:
|
|
case RTC_DAY_OF_MONTH:
|
|
case RTC_MONTH:
|
|
case RTC_YEAR:
|
|
/* if not in set mode, calibrate cmos before
|
|
* reading*/
|
|
if (rtc_running(s)) {
|
|
rtc_update_time(s);
|
|
}
|
|
ret = s->cmos_data[s->cmos_index];
|
|
break;
|
|
case RTC_REG_A:
|
|
if (update_in_progress(s)) {
|
|
s->cmos_data[s->cmos_index] |= REG_A_UIP;
|
|
} else {
|
|
s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
|
|
}
|
|
ret = s->cmos_data[s->cmos_index];
|
|
break;
|
|
case RTC_REG_C:
|
|
ret = s->cmos_data[s->cmos_index];
|
|
qemu_irq_lower(s->irq);
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
if (ret & (REG_C_UF | REG_C_AF)) {
|
|
check_update_timer(s);
|
|
}
|
|
#ifdef TARGET_I386
|
|
if(s->irq_coalesced &&
|
|
(s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
|
|
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
|
|
s->irq_reinject_on_ack_count++;
|
|
s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
|
|
apic_reset_irq_delivered();
|
|
DPRINTF_C("cmos: injecting on ack\n");
|
|
qemu_irq_raise(s->irq);
|
|
if (apic_get_irq_delivered()) {
|
|
s->irq_coalesced--;
|
|
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
|
s->irq_coalesced);
|
|
}
|
|
}
|
|
#endif
|
|
break;
|
|
default:
|
|
ret = s->cmos_data[s->cmos_index];
|
|
break;
|
|
}
|
|
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
|
s->cmos_index, ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
void rtc_set_memory(ISADevice *dev, int addr, int val)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
if (addr >= 0 && addr <= 127)
|
|
s->cmos_data[addr] = val;
|
|
}
|
|
|
|
static void rtc_set_date_from_host(ISADevice *dev)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
struct tm tm;
|
|
|
|
qemu_get_timedate(&tm, 0);
|
|
|
|
s->base_rtc = mktimegm(&tm);
|
|
s->last_update = qemu_get_clock_ns(rtc_clock);
|
|
s->offset = 0;
|
|
|
|
/* set the CMOS date */
|
|
rtc_set_cmos(s, &tm);
|
|
}
|
|
|
|
static int rtc_post_load(void *opaque, int version_id)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
if (version_id <= 2) {
|
|
rtc_set_time(s);
|
|
s->offset = 0;
|
|
check_update_timer(s);
|
|
}
|
|
|
|
#ifdef TARGET_I386
|
|
if (version_id >= 2) {
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
rtc_coalesced_timer_update(s);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_rtc = {
|
|
.name = "mc146818rtc",
|
|
.version_id = 3,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = rtc_post_load,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_BUFFER(cmos_data, RTCState),
|
|
VMSTATE_UINT8(cmos_index, RTCState),
|
|
VMSTATE_UNUSED(7*4),
|
|
VMSTATE_TIMER(periodic_timer, RTCState),
|
|
VMSTATE_INT64(next_periodic_time, RTCState),
|
|
VMSTATE_UNUSED(3*8),
|
|
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
|
VMSTATE_UINT32_V(period, RTCState, 2),
|
|
VMSTATE_UINT64_V(base_rtc, RTCState, 3),
|
|
VMSTATE_UINT64_V(last_update, RTCState, 3),
|
|
VMSTATE_INT64_V(offset, RTCState, 3),
|
|
VMSTATE_TIMER_V(update_timer, RTCState, 3),
|
|
VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void rtc_notify_clock_reset(Notifier *notifier, void *data)
|
|
{
|
|
RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
|
|
int64_t now = *(int64_t *)data;
|
|
|
|
rtc_set_date_from_host(&s->dev);
|
|
periodic_timer_update(s, now);
|
|
check_update_timer(s);
|
|
#ifdef TARGET_I386
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
rtc_coalesced_timer_update(s);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
|
BIOS will read it and start S3 resume at POST Entry */
|
|
static void rtc_notify_suspend(Notifier *notifier, void *data)
|
|
{
|
|
RTCState *s = container_of(notifier, RTCState, suspend_notifier);
|
|
rtc_set_memory(&s->dev, 0xF, 0xFE);
|
|
}
|
|
|
|
static void rtc_reset(void *opaque)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
|
|
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
|
|
check_update_timer(s);
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
#ifdef TARGET_I386
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
s->irq_coalesced = 0;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static const MemoryRegionOps cmos_ops = {
|
|
.read = cmos_ioport_read,
|
|
.write = cmos_ioport_write,
|
|
.impl = {
|
|
.min_access_size = 1,
|
|
.max_access_size = 1,
|
|
},
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
|
|
const char *name, Error **errp)
|
|
{
|
|
ISADevice *isa = ISA_DEVICE(obj);
|
|
RTCState *s = DO_UPCAST(RTCState, dev, isa);
|
|
struct tm current_tm;
|
|
|
|
rtc_update_time(s);
|
|
rtc_get_time(s, ¤t_tm);
|
|
visit_start_struct(v, NULL, "struct tm", name, 0, errp);
|
|
visit_type_int32(v, ¤t_tm.tm_year, "tm_year", errp);
|
|
visit_type_int32(v, ¤t_tm.tm_mon, "tm_mon", errp);
|
|
visit_type_int32(v, ¤t_tm.tm_mday, "tm_mday", errp);
|
|
visit_type_int32(v, ¤t_tm.tm_hour, "tm_hour", errp);
|
|
visit_type_int32(v, ¤t_tm.tm_min, "tm_min", errp);
|
|
visit_type_int32(v, ¤t_tm.tm_sec, "tm_sec", errp);
|
|
visit_end_struct(v, errp);
|
|
}
|
|
|
|
static int rtc_initfn(ISADevice *dev)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
int base = 0x70;
|
|
|
|
s->cmos_data[RTC_REG_A] = 0x26;
|
|
s->cmos_data[RTC_REG_B] = 0x02;
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
s->cmos_data[RTC_REG_D] = 0x80;
|
|
|
|
/* This is for historical reasons. The default base year qdev property
|
|
* was set to 2000 for most machine types before the century byte was
|
|
* implemented.
|
|
*
|
|
* This if statement means that the century byte will be always 0
|
|
* (at least until 2079...) for base_year = 1980, but will be set
|
|
* correctly for base_year = 2000.
|
|
*/
|
|
if (s->base_year == 2000) {
|
|
s->base_year = 0;
|
|
}
|
|
|
|
rtc_set_date_from_host(dev);
|
|
|
|
#ifdef TARGET_I386
|
|
switch (s->lost_tick_policy) {
|
|
case LOST_TICK_SLEW:
|
|
s->coalesced_timer =
|
|
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
|
|
break;
|
|
case LOST_TICK_DISCARD:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
|
|
s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
|
|
check_update_timer(s);
|
|
|
|
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
|
|
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
|
|
|
|
s->suspend_notifier.notify = rtc_notify_suspend;
|
|
qemu_register_suspend_notifier(&s->suspend_notifier);
|
|
|
|
memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
|
|
isa_register_ioport(dev, &s->io, base);
|
|
|
|
qdev_set_legacy_instance_id(&dev->qdev, base, 3);
|
|
qemu_register_reset(rtc_reset, s);
|
|
|
|
object_property_add(OBJECT(s), "date", "struct tm",
|
|
rtc_get_date, NULL, NULL, s, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
|
|
{
|
|
ISADevice *dev;
|
|
RTCState *s;
|
|
|
|
dev = isa_create(bus, "mc146818rtc");
|
|
s = DO_UPCAST(RTCState, dev, dev);
|
|
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
|
qdev_init_nofail(&dev->qdev);
|
|
if (intercept_irq) {
|
|
s->irq = intercept_irq;
|
|
} else {
|
|
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
|
|
}
|
|
return dev;
|
|
}
|
|
|
|
static Property mc146818rtc_properties[] = {
|
|
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
|
|
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
|
|
lost_tick_policy, LOST_TICK_DISCARD),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void rtc_class_initfn(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
|
|
ic->init = rtc_initfn;
|
|
dc->no_user = 1;
|
|
dc->vmsd = &vmstate_rtc;
|
|
dc->props = mc146818rtc_properties;
|
|
}
|
|
|
|
static TypeInfo mc146818rtc_info = {
|
|
.name = "mc146818rtc",
|
|
.parent = TYPE_ISA_DEVICE,
|
|
.instance_size = sizeof(RTCState),
|
|
.class_init = rtc_class_initfn,
|
|
};
|
|
|
|
static void mc146818rtc_register_types(void)
|
|
{
|
|
type_register_static(&mc146818rtc_info);
|
|
}
|
|
|
|
type_init(mc146818rtc_register_types)
|