qemu-e2k/hw/riscv
Bin Meng 60bb5407f0 hw/riscv: Support the official PLIC DT bindings
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:42 +10:00
..
boot.c
Kconfig hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine 2021-05-11 20:02:06 +10:00
meson.build riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
microchip_pfsoc.c
numa.c
opentitan.c hw/riscv: Fix OT IBEX reset vector 2021-05-11 20:02:07 +10:00
riscv_hart.c
shakti_c.c hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_e.c hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] 2021-05-11 20:01:10 +10:00
sifive_u.c hw/riscv: Support the official PLIC DT bindings 2021-06-08 09:59:42 +10:00
spike.c hw/riscv: Support the official CLINT DT bindings 2021-06-08 09:59:42 +10:00
virt.c hw/riscv: Support the official PLIC DT bindings 2021-06-08 09:59:42 +10:00