ce967e2f33
When the HPET enters legacy mode, the IRQ output of the PIT is suppressed and replaced by the HPET timer 0. But the current code to emulate this was broken in many ways. It reset the PIT state after re-enabling, it worked against a stale static PIT structure, and it did not properly saved/restored the IRQ output mask in the PIT vmstate. This patch solves the PIT IRQ control in a different way. On x86, it both redirects the PIT IRQ to the HPET, just like the RTC. But it also keeps the control line from the HPET to the PIT. This allows to disable the PIT QEMU timer when it is not needed. The PIT's view on the control line state is now saved in the same format that qemu-kvm is already using. Note that, in contrast to the suppressed RTC IRQ line, we do not need to save/restore the PIT line state in the HPET. As we trigger a PIT IRQ update via the control line, the line state is reconstructed on mode switch. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* QEMU Emulated HPET support
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*
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* Copyright IBM, Corp. 2008
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*
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* Authors:
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* Beth Kon <bkon@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#ifndef QEMU_HPET_EMUL_H
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#define QEMU_HPET_EMUL_H
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#define HPET_BASE 0xfed00000
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#define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
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#define FS_PER_NS 1000000
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#define HPET_MIN_TIMERS 3
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#define HPET_MAX_TIMERS 32
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#define HPET_NUM_IRQ_ROUTES 32
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#define HPET_LEGACY_PIT_INT 0
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#define HPET_LEGACY_RTC_INT 1
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#define HPET_CFG_ENABLE 0x001
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#define HPET_CFG_LEGACY 0x002
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#define HPET_ID 0x000
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#define HPET_PERIOD 0x004
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#define HPET_CFG 0x010
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#define HPET_STATUS 0x020
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#define HPET_COUNTER 0x0f0
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#define HPET_TN_CFG 0x000
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#define HPET_TN_CMP 0x008
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#define HPET_TN_ROUTE 0x010
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#define HPET_CFG_WRITE_MASK 0x3
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#define HPET_ID_NUM_TIM_SHIFT 8
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#define HPET_ID_NUM_TIM_MASK 0x1f00
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#define HPET_TN_TYPE_LEVEL 0x002
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#define HPET_TN_ENABLE 0x004
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#define HPET_TN_PERIODIC 0x008
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#define HPET_TN_PERIODIC_CAP 0x010
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#define HPET_TN_SIZE_CAP 0x020
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#define HPET_TN_SETVAL 0x040
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#define HPET_TN_32BIT 0x100
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#define HPET_TN_INT_ROUTE_MASK 0x3e00
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#define HPET_TN_FSB_ENABLE 0x4000
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#define HPET_TN_FSB_CAP 0x8000
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#define HPET_TN_CFG_WRITE_MASK 0x7f4e
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#define HPET_TN_INT_ROUTE_SHIFT 9
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#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
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#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
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struct hpet_fw_entry
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{
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uint32_t event_timer_block_id;
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uint64_t address;
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uint16_t min_tick;
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uint8_t page_prot;
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} QEMU_PACKED;
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struct hpet_fw_config
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{
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uint8_t count;
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struct hpet_fw_entry hpet[8];
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} QEMU_PACKED;
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extern struct hpet_fw_config hpet_cfg;
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#endif
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