d578ca6cbb
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-11-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
106 lines
3.7 KiB
PHP
106 lines
3.7 KiB
PHP
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool gen_fff(DisasContext *ctx, arg_fff *a,
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void (*func)(TCGv, TCGv_env, TCGv, TCGv))
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{
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func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
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return true;
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}
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static bool gen_ff(DisasContext *ctx, arg_ff *a,
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void (*func)(TCGv, TCGv_env, TCGv))
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{
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func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
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return true;
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}
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static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
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void (*func)(TCGv, TCGv_env, TCGv, TCGv, TCGv, TCGv_i32),
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int flag)
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{
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TCGv_i32 tflag = tcg_constant_i32(flag);
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func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
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cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
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return true;
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}
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static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
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{
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tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
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return true;
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}
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static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
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{
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tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
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return true;
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}
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static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
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{
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tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
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gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
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return true;
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}
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static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
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{
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tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
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return true;
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}
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static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
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{
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tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
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gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
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return true;
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}
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static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
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{
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tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
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return true;
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}
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TRANS(fadd_s, gen_fff, gen_helper_fadd_s)
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TRANS(fadd_d, gen_fff, gen_helper_fadd_d)
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TRANS(fsub_s, gen_fff, gen_helper_fsub_s)
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TRANS(fsub_d, gen_fff, gen_helper_fsub_d)
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TRANS(fmul_s, gen_fff, gen_helper_fmul_s)
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TRANS(fmul_d, gen_fff, gen_helper_fmul_d)
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TRANS(fdiv_s, gen_fff, gen_helper_fdiv_s)
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TRANS(fdiv_d, gen_fff, gen_helper_fdiv_d)
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TRANS(fmax_s, gen_fff, gen_helper_fmax_s)
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TRANS(fmax_d, gen_fff, gen_helper_fmax_d)
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TRANS(fmin_s, gen_fff, gen_helper_fmin_s)
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TRANS(fmin_d, gen_fff, gen_helper_fmin_d)
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TRANS(fmaxa_s, gen_fff, gen_helper_fmaxa_s)
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TRANS(fmaxa_d, gen_fff, gen_helper_fmaxa_d)
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TRANS(fmina_s, gen_fff, gen_helper_fmina_s)
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TRANS(fmina_d, gen_fff, gen_helper_fmina_d)
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TRANS(fscaleb_s, gen_fff, gen_helper_fscaleb_s)
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TRANS(fscaleb_d, gen_fff, gen_helper_fscaleb_d)
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TRANS(fsqrt_s, gen_ff, gen_helper_fsqrt_s)
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TRANS(fsqrt_d, gen_ff, gen_helper_fsqrt_d)
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TRANS(frecip_s, gen_ff, gen_helper_frecip_s)
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TRANS(frecip_d, gen_ff, gen_helper_frecip_d)
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TRANS(frsqrt_s, gen_ff, gen_helper_frsqrt_s)
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TRANS(frsqrt_d, gen_ff, gen_helper_frsqrt_d)
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TRANS(flogb_s, gen_ff, gen_helper_flogb_s)
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TRANS(flogb_d, gen_ff, gen_helper_flogb_d)
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TRANS(fclass_s, gen_ff, gen_helper_fclass_s)
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TRANS(fclass_d, gen_ff, gen_helper_fclass_d)
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TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
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TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
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TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
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TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
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TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,
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float_muladd_negate_product | float_muladd_negate_c)
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TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,
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float_muladd_negate_product | float_muladd_negate_c)
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TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)
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TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)
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