a10b9d93ec
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
16 lines
296 B
Makefile
16 lines
296 B
Makefile
# Default configuration for riscv32-softmmu
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# Uncomment the following lines to disable these optional devices:
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#
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#CONFIG_PCI_DEVICES=n
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CONFIG_SEMIHOSTING=y
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CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
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# Boards:
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#
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CONFIG_SPIKE=y
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CONFIG_SIFIVE_E=y
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CONFIG_SIFIVE_U=y
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CONFIG_RISCV_VIRT=y
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CONFIG_OPENTITAN=y
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