661 lines
20 KiB
C
661 lines
20 KiB
C
#include "qemu/osdep.h"
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#include "qemu.h"
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#include "exec/log.h"
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#include "translate.h"
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static inline void gen_lcnt_dec(TCGv_i64 ret, TCGv_i64 lsr)
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{
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 lcnt = tcg_temp_new_i32();
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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TCGv_i32 t4 = tcg_temp_new_i32();
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TCGv_i32 t5 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(lcnt, lsr);
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tcg_gen_subi_i32(t0, lcnt, 1);
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tcg_gen_movcond_i32(TCG_COND_EQ, t1, lcnt, zero, zero, t0);
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/* overflow bit */
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tcg_gen_extrh_i64_i32(t2, lsr);
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tcg_gen_setcondi_i32(TCG_COND_EQ, t3, lcnt, 1);
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tcg_gen_shli_i32(t4, t3, LSR_OVER_OFF - 32);
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tcg_gen_or_i32(t5, t2, t4);
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tcg_gen_concat_i32_i64(ret, t1, t5);
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tcg_temp_free_i32(t5);
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tcg_temp_free_i32(t4);
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tcg_temp_free_i32(t3);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(lcnt);
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tcg_temp_free_i32(zero);
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}
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static void gen_movcond_flag_i32(TCGv_i32 ret, int flag, TCGv_i32 cond,
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TCGv_i32 v1, TCGv_i32 v2)
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{
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TCGv_i32 one = tcg_const_i32(1);
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TCGCond c;
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switch (flag) {
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case 0x00:
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c = TCG_COND_NEVER;
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break;
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case 0x01:
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c = TCG_COND_EQ;
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break;
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case 0x02:
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c = TCG_COND_NE;
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break;
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case 0x03:
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c = TCG_COND_ALWAYS;
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break;
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default:
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g_assert_not_reached();
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break;
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}
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tcg_gen_movcond_i32(c, ret, cond, one, v1, v2);
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tcg_temp_free_i32(one);
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}
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static inline void gen_movcond_flag_i64(TCGv_i64 ret, int flag, TCGv_i64 cond,
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TCGv_i64 v1, TCGv_i64 v2)
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{
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TCGv_i64 one = tcg_const_i64(1);
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TCGCond c;
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switch (flag) {
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case 0x00:
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c = TCG_COND_NEVER;
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break;
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case 0x01:
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c = TCG_COND_EQ;
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break;
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case 0x02:
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c = TCG_COND_NE;
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break;
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case 0x03:
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c = TCG_COND_ALWAYS;
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break;
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default:
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g_assert_not_reached();
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break;
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}
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tcg_gen_movcond_i64(c, ret, cond, one, v1, v2);
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tcg_temp_free_i64(one);
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}
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static inline void gen_cur_dec(TCGv_i32 ret, int cond, TCGv_i32 cur, int n,
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TCGv_i32 size)
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{
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TCGv_i32 c = tcg_temp_new_i32();
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TCGv_i32 t0 = tcg_const_i32(n);
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(c, e2k_cs.cond);
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gen_helper_cur_dec(t1, cpu_env, cur, t0, size);
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gen_movcond_flag_i32(ret, cond, c, t1, cur);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(c);
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}
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void e2k_win_commit(DisasContext *dc)
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{
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TCGv_i32 cond = tcg_temp_new_i32();
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// Change windowing registers after commit is done.
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uint32_t ss = dc->bundle.ss;
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// unsigned int vfdi = (ss & 0x04000000) >> 26;
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// unsigned int abg = (ss & 0x01800000) >> 23;
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int alc = GET_FIELD(ss, 16, 17);
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int abp = GET_FIELD(ss, 18, 19);
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int abn = GET_FIELD(ss, 21, 22);
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int abg = GET_FIELD(ss, 23, 24);
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tcg_gen_trunc_tl_i32(cond, e2k_cs.cond);
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if (alc) {
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TCGv_i64 t0 = tcg_temp_new_i64();
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gen_lcnt_dec(t0, e2k_cs.lsr);
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gen_movcond_flag_i64(e2k_cs.lsr, alc, e2k_cs.cond, t0, e2k_cs.lsr);
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tcg_temp_free_i64(t0);
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}
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if (abp) {
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gen_cur_dec(e2k_cs.pcur, abp, e2k_cs.pcur, 1, e2k_cs.psize);
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}
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if (abn) {
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gen_cur_dec(e2k_cs.bcur, abn, e2k_cs.bcur, 2, e2k_cs.bsize);
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}
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switch(abg) {
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case 0x00:
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break;
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case 0x01:
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/* TODO */
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abort();
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break;
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case 0x02:
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/* TODO */
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abort();
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break;
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default:
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/* FIXME: exception or nop? */
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break;
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}
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tcg_temp_free_i32(cond);
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}
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static inline void gen_is_last_iter(TCGv ret)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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e2k_gen_lcnt(t0);
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tcg_gen_setcondi_tl(TCG_COND_LTU, t1, t0, 2);
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tcg_gen_extract_tl(t2, e2k_cs.lsr, LSR_VLC_OFF, 1);
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tcg_gen_and_tl(ret, t1, t2);
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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static inline void gen_is_loop_end(TCGv ret)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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e2k_gen_ecnt(t0);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t1, t0, 0);
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gen_is_last_iter(t2);
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tcg_gen_and_tl(ret, t1, t2);
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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static void gen_cs0(DisasContext *dc)
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{
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typedef enum {
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NOTHING,
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IBRANCH,
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PREF,
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PUTTSD,
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DONE,
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HRET,
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GLAUNCH,
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DISP,
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SDISP,
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GETTSD,
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LDISP,
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RETURN
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} cs0_type;
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static cs0_type cs0_ops[4][4] = {
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{IBRANCH, PREF, PUTTSD, DONE},
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{DISP, NOTHING, SDISP, GETTSD},
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{DISP, LDISP, SDISP, GETTSD},
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{DISP, NOTHING, SDISP, RETURN}
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};
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const UnpackedBundle *bundle = &dc->bundle;
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uint32_t cs0 = bundle->cs0;
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unsigned int ctpr = (cs0 & 0xc0000000) >> 30;
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unsigned int ctp_opc = (cs0 & 0x30000000) >> 28;
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unsigned int param_type = (cs0 & 0x00000007);
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cs0_type type = cs0_ops[ctpr][ctp_opc];
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if (type == RETURN && param_type == 1) {
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type = GETTSD;
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} else if (type == DONE) {
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if (param_type == 3) {
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type = HRET;
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} else if (param_type == 4) {
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type = GLAUNCH;
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}
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}
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if (type == IBRANCH || type == DONE || type == HRET || type == GLAUNCH) {
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/* IBRANCH, DONE, HRET and GLAUNCH are special because they require SS
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to be properly encoded. */
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if (!bundle->ss_present || (bundle->ss & 0x00000c00))
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{
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// TODO: exeption invalid bundle
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abort();
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/* Don't output either of the aforementioned instructions under "never"
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condition. Don't disassemble CS0 being a part of HCALL. Unlike ldis
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HCALL is currently disassembled on behalf of CS1. */
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} else if ((bundle->ss & 0x1ff)
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&& !(bundle->cs1_present
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/* CS1.opc == CALL */
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&& (bundle->cs1 & 0xf0000000) >> 28 == 5
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/* CS1.param.ctopc == HCALL */
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&& (bundle->cs1 & 0x380) >> 7 == 2))
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{
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if (type == IBRANCH) {
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/* C0F2 has `disp' field. In `C0F1' it's called `param'. Is this
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the only difference between these two formats? Funnily enough,
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DONE is also C0F2 and thus has `disp', though it obviously
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makes no sense for it. */
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unsigned int disp = (cs0 & 0x0fffffff);
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/* Calculate a signed displacement in bytes. */
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int sdisp = ((int) (disp << 4)) >> 1;
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dc->jmp.dest = dc->pc + sdisp;
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dc->base.is_jmp = DISAS_JUMP_STATIC;
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}
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}
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} else {
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/* Note that according to Table B.4.1 it's possible to obtain
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` gettsd %ctpr{1,2} with an invalid value for CS0.param.type. */
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if (type == GETTSD && param_type != 1) {
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// invalid
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abort();
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}
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int ipd = GET_FIELD(bundle->ss, 30, 31);
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if (type == DISP || type == LDISP) {
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unsigned int disp = GET_FIELD(cs0, 0, 27);
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/* Calculate a signed displacement in bytes. */
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int sdisp = ((int) (disp << 4)) >> 1;
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uint64_t reg = (dc->pc + sdisp) |
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((uint64_t) CTPR_TAG_DISP << CTPR_TAG_OFF) |
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((uint64_t) ipd << CTPR_IPD_OFF);
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if (type == LDISP) {
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reg |= (uint64_t) CTPR_OPC_LDISP << CTPR_OPC_OFF;
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}
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tcg_gen_movi_tl(e2k_cs.ctprs[ctpr], reg);
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} else if (type == SDISP) {
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unsigned int disp = GET_FIELD(cs0, 0, 27) << 11;
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/* FIXME: trap address */
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target_ulong base = ((uint64_t) 0xe2 << 40) | disp;
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uint64_t reg = (dc->pc + base) |
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((uint64_t) CTPR_TAG_SDISP << CTPR_TAG_OFF) |
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((uint64_t) ipd << CTPR_IPD_OFF);
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tcg_gen_movi_tl(e2k_cs.ctprs[ctpr], reg);
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}
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/* Note that RETURN is said to be COPF1. I can't understand what its
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`CS0.param' is needed for: all of the bits except the three
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lowermost ones are undefined, while the latter also known as "type"
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field should be filled in with zeroes. */
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if (type == RETURN) {
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uint64_t reg = ((uint64_t) CTPR_TAG_RETURN << CTPR_TAG_OFF) |
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((uint64_t) ipd << CTPR_IPD_OFF);
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tcg_gen_movi_tl(e2k_cs.ctprs[ctpr], reg);
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}
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/* GETTSD has as meaningless `CS0.param' as RETURN. The only
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difference is that its `CS0.param.type' should be equal to `1'. I
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wonder if I should check for that and output something like
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"invalid gettsd" if this turns out not to be the case . . . */
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if (type == GETTSD) {
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// TODO
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}
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if (type == SDISP) {
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// my_printf (", 0x%x", cs0 & 0x1f);
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} else if (type == DISP
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|| type == LDISP
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|| type == PUTTSD)
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{
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// unsigned int disp = (cs0 & 0x0fffffff);
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// int sgnd_disp = ((int) (disp << 4)) >> 1;
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/* PUTTSD obviously doesn't take %ctpr{j} parameter. TODO: beware of
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an optional predicate which may control its execution which is
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encoded via `SS.ctcond.psrc' and `SS.ts_opc == PUTTSDC{P,N}' in
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case of `SS.type == 1' (see C.21.4). I wonder if `ct %ctpr<j>'
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encoded in `SS.ctop' under the same `SS.ctcond' takes an effect in
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such a case. */
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// my_printf ("%s0x%llx", type == PUTTSD ? "" : ", ",
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/* FIXME: this way I ensure that it'll work correctly
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both on 32 and 64-bit hosts. */
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// (unsigned long long) (instr_addr + sgnd_disp));
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}
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if (type == PREF) {
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// unsigned int pdisp = (bundle->cs0 & 0x0ffffff0) >> 4;
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// unsigned int ipd = (bundle->cs0 & 0x00000008) >> 3;
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// unsigned int prefr = bundle->cs0 & 0x00000007;
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}
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}
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}
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static void gen_cs1(DisasContext *dc)
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{
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enum {
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SETR0,
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SETR1,
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SETEI,
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WAIT,
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SETBR,
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CALL,
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MAS_OPC,
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FLUSHR,
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BG
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};
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const UnpackedBundle *bundle = &dc->bundle;
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unsigned int cs1 = bundle->cs1;
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unsigned int opc = (cs1 & 0xf0000000) >> 28;
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if (opc == SETR0 || opc == SETR1 || opc == SETBR) {
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unsigned int setbp = (cs1 & 0x08000000) >> 27;
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unsigned int setbn = (cs1 & 0x04000000) >> 26;
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/* Try to follow the same order of these instructions as in LDIS.
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Presumably `vfrpsz' should come first, while `setbp' should be placed
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between `setwd' and `setbn', but this is to be verified. I don't have
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a binary with these commands by hand right now. */
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if (opc == SETR1) {
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if (! bundle->lts_present[0]) {
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// my_printf ("<bogus vfrpsz>");
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} else {
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/* Find out if VFRPSZ is always encoded together with SETWD. This
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seems to be the case even if no SETWD has been explicitly
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specified. */
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// unsigned int rpsz = (bundle->lts[0] & 0x0001f000) >> 12;
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// my_printf ("vfrpsz rpsz = 0x%x", rpsz);
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}
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}
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// FIXME: Should windowing registers be precomputed or not?
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if (opc == SETR0 || opc == SETR1) {
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if (! bundle->lts_present[0]) {
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// TODO: <bogus setwd>
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abort();
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} else {
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uint32_t lts0 = bundle->lts[0];
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int wsz = GET_FIELD(lts0, 5, 11);
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TCGv_i32 t0 = tcg_const_i32(lts0);
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tcg_gen_movi_i32(e2k_cs.wsize, wsz * 2);
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tcg_temp_free_i32(t0);
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}
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}
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if (setbn) {
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int rbs = GET_FIELD(cs1, BR_RBS_OFF, BR_RBS_END);
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int rsz = GET_FIELD(cs1, BR_RSZ_OFF, BR_RSZ_END);
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int rcur = GET_FIELD(cs1, BR_RCUR_OFF, BR_RCUR_END);
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tcg_gen_movi_i32(e2k_cs.boff, rbs * 2);
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tcg_gen_movi_i32(e2k_cs.bsize, (rsz + 1) * 2);
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tcg_gen_movi_i32(e2k_cs.bcur, rcur * 2);
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}
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if (setbp) {
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int psz = GET_FIELD(cs1, BR_PSZ_OFF, BR_PSZ_END);
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tcg_gen_movi_i32(e2k_cs.psize, psz);
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tcg_gen_movi_i32(e2k_cs.pcur, 0);
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}
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} else if (opc == SETEI) {
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/* Verify that CS1.param.sft = CS1.param[27] is equal to zero as required
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in C.14.3. */
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unsigned int sft = (cs1 & 0x08000000) >> 27;
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// unsigned int eir = (cs1 & 0x000000ff);
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if (sft) {
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// my_printf ("%s", mcpu >= 2 ? "setsft" : "unimp");
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} else {
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// my_printf ("setei 0x%x", eir);
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}
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} else if (opc == WAIT) {
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// unsigned int ma_c = (cs1 & 0x00000020) >> 5;
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// unsigned int fl_c = (cs1 & 0x00000010) >> 4;
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unsigned int ld_c = (cs1 & 0x00000008) >> 3;
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unsigned int st_c = (cs1 & 0x00000004) >> 2;
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// unsigned int all_e = (cs1 & 0x00000002) >> 1;
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// unsigned int all_c = cs1 & 0x00000001;
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if (dc->version >= 5) {
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/* `sa{l,s}' fields are `elbrus-v5'-specific. Each of them makes sense
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only in the presence of `{ld,st}_c == 1' respectively. */
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if (ld_c) {
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// unsigned int sal = (cs1 & 0x00000100) >> 8;
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// my_printf ("sal = %d, ", sal);
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}
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if (st_c) {
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// unsigned int sas = (cs1 & 0x00000080) >> 7;
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// my_printf ("sas = %d, ", sas);
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}
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}
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if (dc->version >= 2) {
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/* `trap' field was introduced starting from `elbrus-v2'. */
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// unsigned int trap = (cs1 & 0x00000040) >> 6;
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// my_printf ("trap = %d, ", trap);
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}
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// my_printf ("ma_c = %d, fl_c = %d, ld_c = %d, st_c = %d, all_e = %d, "
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// "all_c = %d", ma_c, fl_c, ld_c, st_c, all_e, all_c);
|
|
} else if (opc == CALL) {
|
|
unsigned int ctop = (bundle->ss & 0x00000c00) >> 10;
|
|
/* In C.17.4 it's said that other bits in CS1.param except for the
|
|
seven lowermost ones are ignored. */
|
|
unsigned int wbs = cs1 & 0x7f;
|
|
|
|
if (ctop) {
|
|
tcg_gen_movi_i32(e2k_cs.call_wbs, wbs);
|
|
// my_printf ("call %%ctpr%d, wbs = 0x%x", ctop, wbs);
|
|
// print_ctcond (info, instr->ss & 0x1ff);
|
|
} else {
|
|
unsigned int cs1_ctopc = (cs1 & 0x380) >> 7;
|
|
/* CS1.param.ctpopc == HCALL. CS0 is required to encode HCALL. */
|
|
if (cs1_ctopc == 2 && bundle->cs0_present) {
|
|
unsigned int cs0 = bundle->cs0;
|
|
unsigned int cs0_opc = (cs0 & 0xf0000000) >> 28;
|
|
/* CS0.opc == HCALL, which means
|
|
CS0.opc.ctpr == CS0.opc.ctp_opc == 0 */
|
|
if (cs0_opc == 0) {
|
|
// unsigned int hdisp = (cs0 & 0x1e) >> 1;
|
|
// my_printf ("hcall 0x%x, wbs = 0x%x", hdisp, wbs);
|
|
// print_ctcond (info, instr->ss & 0x1ff);
|
|
}
|
|
} else {
|
|
// my_printf ("<bogus call>");
|
|
}
|
|
}
|
|
} else if (opc == MAS_OPC) {
|
|
/* Note that LDIS doesn't print it out as a standalone instruction. */
|
|
// unsigned int mas = cs1 & 0x0fffffff;
|
|
|
|
// my_printf ("mas 0x%x", mas);
|
|
} else if (opc == FLUSHR) {
|
|
/* . . . these stupid engineers off! FLUSHR seems to be responsible for
|
|
encoding both `flushr' and `flushc'. Moreover, according to their
|
|
logic it should be possible to encode them simultaneously. */
|
|
|
|
/* Check for `CS1.param.flr'. */
|
|
if (cs1 & 0x00000001) {
|
|
// my_printf ("flushr");
|
|
}
|
|
|
|
/* Check for `CS1.param.flc'. */
|
|
if (cs1 & 0x00000002) {
|
|
// my_printf ("flushc");
|
|
}
|
|
} else if (opc == BG) {
|
|
/* Hopefully, `vfbg' is the only instruction encoded by BG. I'm currently
|
|
unable to find other ones in `iset-v5.single' at least . . . */
|
|
// unsigned int chkm4 = (cs1 & 0x00010000) >> 16;
|
|
// unsigned int dmask = (cs1 & 0x0000ff00) >> 8;
|
|
// unsigned int umsk = cs1 & 0x000000ff;
|
|
|
|
/* Print its fields in the order proposed in C.14.10. */
|
|
// my_printf ("vfbg umask = 0x%x, dmask = 0x%x, chkm4 = 0x%x",
|
|
// umsk, dmask, chkm4);
|
|
} else {
|
|
// my_printf ("unimp");
|
|
abort();
|
|
}
|
|
}
|
|
|
|
static void gen_jmp(DisasContext *dc)
|
|
{
|
|
unsigned int psrc = GET_FIELD(dc->bundle.ss, 0, 4);
|
|
unsigned int cond_type = GET_FIELD(dc->bundle.ss, 5, 8);
|
|
unsigned int ctpr = GET_FIELD(dc->bundle.ss, 10, 11);
|
|
|
|
/* TODO: check CPU behavior if present ibranch and ctpr is not zero */
|
|
|
|
/* TODO: different kinds of ct */
|
|
if (ctpr != 0) {
|
|
dc->jump_ctpr = ctpr;
|
|
dc->base.is_jmp = DISAS_JUMP;
|
|
}
|
|
|
|
if (cond_type == 1) {
|
|
tcg_gen_movi_tl(e2k_cs.cond, 1);
|
|
} else if (cond_type > 1) {
|
|
switch (dc->base.is_jmp) {
|
|
case DISAS_JUMP:
|
|
dc->base.is_jmp = DISAS_BRANCH;
|
|
break;
|
|
case DISAS_JUMP_STATIC:
|
|
dc->base.is_jmp = DISAS_BRANCH_STATIC;
|
|
break;
|
|
default:
|
|
/* FIXME: what action to do? */
|
|
g_assert_not_reached();
|
|
break;
|
|
}
|
|
|
|
/* TODO: single assign */
|
|
TCGv preg = tcg_temp_new();
|
|
TCGv loop_end = tcg_temp_new();
|
|
TCGv not_loop_end = tcg_temp_new();
|
|
TCGv_i64 t0 = tcg_temp_new_i64();
|
|
|
|
e2k_gen_preg(t0, psrc);
|
|
tcg_gen_trunc_i64_tl(preg, t0);
|
|
gen_is_loop_end(loop_end);
|
|
tcg_gen_setcondi_tl(TCG_COND_NE, not_loop_end, loop_end, 1);
|
|
|
|
switch (cond_type) {
|
|
case 0x2:
|
|
case 0x6:
|
|
case 0xf:
|
|
tcg_gen_mov_tl(e2k_cs.cond, preg);
|
|
break;
|
|
case 0x3:
|
|
case 0x7:
|
|
case 0xe:
|
|
tcg_gen_setcondi_tl(TCG_COND_NE, e2k_cs.cond, preg, 1);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (cond_type) {
|
|
case 0x4:
|
|
tcg_gen_mov_tl(e2k_cs.cond, loop_end);
|
|
break;
|
|
case 0x5:
|
|
tcg_gen_mov_tl(e2k_cs.cond, not_loop_end);
|
|
break;
|
|
case 0x6:
|
|
case 0xe:
|
|
tcg_gen_or_tl(e2k_cs.cond, e2k_cs.cond, loop_end);
|
|
break;
|
|
case 0x7:
|
|
case 0xf:
|
|
tcg_gen_and_tl(e2k_cs.cond, e2k_cs.cond, not_loop_end);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (cond_type == 8) {
|
|
// %MLOCK
|
|
/* It's not clearly said in C.17.1.2 of iset-vX.single if the uppermost
|
|
fourth bit in `psrc' has any meaning at all. */
|
|
if (psrc & 0xf) {
|
|
// static const int conv[] = {0, 1, 3, 4};
|
|
int i;
|
|
|
|
// %dt_al
|
|
for (i = 0; i < 4; i++) {
|
|
if (psrc & (1 << i)) {
|
|
// i
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* `lock_cond || pl_cond' control transfer conditions. */
|
|
if (cond_type == 9) {
|
|
unsigned int type = (psrc & 0x18) >> 3;
|
|
if (type == 0) {
|
|
// static const int cmp_num_to_alc[] = {0, 1, 3, 4};
|
|
// unsigned int cmp_num = (psrc & 0x6) >> 1;
|
|
// unsigned int neg = psrc & 0x1;
|
|
|
|
// my_printf ("%%MLOCK || %s%%cmp%d", neg ? "~" : "",
|
|
// cmp_num_to_alc[cmp_num]);
|
|
} else if (type == 1) {
|
|
// unsigned int cmp_jk = (psrc & 0x4) >> 2;
|
|
// unsigned int negj = (psrc & 0x2) >> 1;
|
|
// unsigned int negk = psrc & 0x1;
|
|
|
|
// my_printf ("%%MLOCK || %s%%cmp%d || %s%%cmp%d",
|
|
// negj ? "~" : "", cmp_jk == 0 ? 0 : 3,
|
|
// negk ? "~" : "", cmp_jk == 0 ? 1 : 4);
|
|
} else if (type == 2) {
|
|
// unsigned int clp_num = (psrc & 0x6) >> 1;
|
|
// unsigned int neg = psrc & 0x1;
|
|
|
|
// "%%MLOCK || %s%%clp%d", neg ? "~" : "", clp_num
|
|
}
|
|
}
|
|
|
|
if (cond_type >= 0xa && cond_type <= 0xd) {
|
|
// reserved condition type
|
|
qemu_log_mask(LOG_UNIMP, "Undefined control transfer type %#x\n", cond_type);
|
|
abort();
|
|
}
|
|
|
|
|
|
tcg_temp_free_i64(t0);
|
|
tcg_temp_free(not_loop_end);
|
|
tcg_temp_free(loop_end);
|
|
tcg_temp_free(preg);
|
|
}
|
|
}
|
|
|
|
void e2k_control_gen(DisasContext *dc)
|
|
{
|
|
if (dc->bundle.cs0_present) {
|
|
gen_cs0(dc);
|
|
}
|
|
|
|
if (dc->bundle.cs1_present) {
|
|
gen_cs1(dc);
|
|
}
|
|
|
|
if (dc->bundle.ss_present) {
|
|
gen_jmp(dc);
|
|
}
|
|
}
|