qemu-e2k/include/hw
Ben Widawsky 6364adacdf hw/cxl/device: Implement the CAP array (8.2.8.1-2)
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.

Endianness and alignment are managed by softmmu memory core.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-05-13 06:13:36 -04:00
..
acpi
adc
arm
audio
block
char
core
cpu
cris
cxl hw/cxl/device: Implement the CAP array (8.2.8.1-2) 2022-05-13 06:13:36 -04:00
display
dma
firmware
gpio
hyperv
i2c
i386
ide
input
intc
ipack
ipmi
isa
kvm
m68k
mem
mips
misc
net
nubus
nvram
pci
pci-bridge
pci-host
ppc
rdma
remote
riscv
rtc
rx
s390x
scsi
sd
sensor
sh4
southbridge
sparc
ssi
timer
tricore
usb
vfio
virtio
watchdog
xen
xtensa
boards.h
clock.h
elf_ops.h
fw-path-provider.h
hotplug.h
hw.h
ide.h
irq.h
loader-fit.h
loader.h
nmi.h
or-irq.h
pcmcia.h
platform-bus.h
ptimer.h
qdev-clock.h
qdev-core.h
qdev-dma.h
qdev-properties-system.h
qdev-properties.h
register.h
registerfields.h
resettable.h
stream.h
sysbus.h
usb.h
vmstate-if.h