470 lines
13 KiB
C
470 lines
13 KiB
C
/*
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* TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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*
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* Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "i2c.h"
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#include "omap.h"
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struct omap_i2c_s {
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qemu_irq irq;
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qemu_irq drq[2];
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i2c_bus *bus;
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uint8_t revision;
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uint8_t mask;
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uint16_t stat;
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uint16_t dma;
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uint16_t count;
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int count_cur;
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uint32_t fifo;
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int rxlen;
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int txlen;
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uint16_t control;
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uint16_t addr[2];
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uint8_t divider;
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uint8_t times[2];
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uint16_t test;
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};
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#define OMAP2_INTR_REV 0x34
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#define OMAP2_GC_REV 0x34
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static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
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{
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qemu_set_irq(s->irq, s->stat & s->mask);
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if ((s->dma >> 15) & 1) /* RDMA_EN */
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qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
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if ((s->dma >> 7) & 1) /* XDMA_EN */
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qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
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}
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static void omap_i2c_fifo_run(struct omap_i2c_s *s)
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{
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int ack = 1;
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if (!i2c_bus_busy(s->bus))
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return;
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if ((s->control >> 2) & 1) { /* RM */
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->txlen)
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0);
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s->stat |= 1 << 4; /* XRDY */
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} else {
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while (s->rxlen < 4)
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->stat |= 1 << 3; /* RRDY */
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}
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} else {
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if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->count_cur && s->txlen) {
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0);
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s->count_cur --;
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}
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if (ack && s->count_cur)
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s->stat |= 1 << 4; /* XRDY */
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else
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s->stat &= ~(1 << 4); /* XRDY */
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if (!s->count_cur) {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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} else {
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while (s->count_cur && s->rxlen < 4) {
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->count_cur --;
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}
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if (s->rxlen)
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s->stat |= 1 << 3; /* RRDY */
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else
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s->stat &= ~(1 << 3); /* RRDY */
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}
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if (!s->count_cur) {
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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}
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s->stat |= (!ack) << 1; /* NACK */
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if (!ack)
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s->control &= ~(1 << 1); /* STP */
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}
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void omap_i2c_reset(struct omap_i2c_s *s)
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{
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s->mask = 0;
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s->stat = 0;
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s->dma = 0;
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s->count = 0;
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s->count_cur = 0;
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s->fifo = 0;
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s->rxlen = 0;
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s->txlen = 0;
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s->control = 0;
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s->addr[0] = 0;
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s->addr[1] = 0;
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s->divider = 0;
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s->times[0] = 0;
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s->times[1] = 0;
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s->test = 0;
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}
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static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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uint16_t ret;
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switch (offset) {
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case 0x00: /* I2C_REV */
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return s->revision; /* REV */
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case 0x04: /* I2C_IE */
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return s->mask;
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case 0x08: /* I2C_STAT */
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return s->stat | (i2c_bus_busy(s->bus) << 12);
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case 0x0c: /* I2C_IV */
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if (s->revision >= OMAP2_INTR_REV)
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break;
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ret = ffs(s->stat & s->mask);
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if (ret)
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s->stat ^= 1 << (ret - 1);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x10: /* I2C_SYSS */
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return (s->control >> 15) & 1; /* I2C_EN */
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case 0x14: /* I2C_BUF */
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return s->dma;
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case 0x18: /* I2C_CNT */
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return s->count_cur; /* DCOUNT */
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case 0x1c: /* I2C_DATA */
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ret = 0;
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if (s->control & (1 << 14)) { /* BE */
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ret |= ((s->fifo >> 0) & 0xff) << 8;
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ret |= ((s->fifo >> 8) & 0xff) << 0;
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} else {
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ret |= ((s->fifo >> 8) & 0xff) << 8;
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ret |= ((s->fifo >> 0) & 0xff) << 0;
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}
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if (s->rxlen == 1) {
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s->stat |= 1 << 15; /* SBD */
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s->rxlen = 0;
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} else if (s->rxlen > 1) {
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if (s->rxlen > 2)
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s->fifo >>= 16;
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s->rxlen -= 2;
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} else
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/* XXX: remote access (qualifier) error - what's that? */;
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if (!s->rxlen) {
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s->stat &= ~(1 << 3); /* RRDY */
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if (((s->control >> 10) & 1) && /* MST */
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((~s->control >> 9) & 1)) { /* TRX */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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s->stat &= ~(1 << 11); /* ROVR */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x20: /* I2C_SYSC */
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return 0;
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case 0x24: /* I2C_CON */
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return s->control;
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case 0x28: /* I2C_OA */
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return s->addr[0];
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case 0x2c: /* I2C_SA */
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return s->addr[1];
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case 0x30: /* I2C_PSC */
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return s->divider;
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case 0x34: /* I2C_SCLL */
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return s->times[0];
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case 0x38: /* I2C_SCLH */
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return s->times[1];
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case 0x3c: /* I2C_SYSTEST */
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if (s->test & (1 << 15)) { /* ST_EN */
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s->test ^= 0xa;
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return s->test;
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} else
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return s->test & ~0x300f;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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int nack;
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switch (offset) {
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case 0x00: /* I2C_REV */
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case 0x0c: /* I2C_IV */
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case 0x10: /* I2C_SYSS */
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OMAP_RO_REG(addr);
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return;
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case 0x04: /* I2C_IE */
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s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
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break;
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case 0x08: /* I2C_STAT */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_RO_REG(addr);
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return;
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}
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/* RRDY and XRDY are reset by hardware. (in all versions???) */
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s->stat &= ~(value & 0x27);
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omap_i2c_interrupts_update(s);
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break;
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case 0x14: /* I2C_BUF */
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s->dma = value & 0x8080;
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if (value & (1 << 15)) /* RDMA_EN */
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s->mask &= ~(1 << 3); /* RRDY_IE */
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if (value & (1 << 7)) /* XDMA_EN */
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s->mask &= ~(1 << 4); /* XRDY_IE */
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break;
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case 0x18: /* I2C_CNT */
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s->count = value; /* DCOUNT */
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break;
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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}
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s->fifo <<= 16;
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s->txlen += 2;
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if (s->control & (1 << 14)) { /* BE */
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s->fifo |= ((value >> 8) & 0xff) << 8;
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s->fifo |= ((value >> 0) & 0xff) << 0;
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} else {
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s->fifo |= ((value >> 0) & 0xff) << 8;
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s->fifo |= ((value >> 8) & 0xff) << 0;
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}
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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break;
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case 0x20: /* I2C_SYSC */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_BAD_REG(addr);
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return;
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}
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if (value & 2)
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omap_i2c_reset(s);
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break;
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case 0x24: /* I2C_CON */
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s->control = value & 0xcf87;
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if (~value & (1 << 15)) { /* I2C_EN */
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if (s->revision < OMAP2_INTR_REV)
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omap_i2c_reset(s);
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break;
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}
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if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
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fprintf(stderr, "%s: I^2C slave mode not supported\n",
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__FUNCTION__);
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break;
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}
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if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
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fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
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__FUNCTION__);
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break;
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}
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if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
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nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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s->fifo = 0;
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if (nack)
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s->control &= ~(1 << 1); /* STP */
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else {
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s->count_cur = s->count;
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omap_i2c_fifo_run(s);
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}
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omap_i2c_interrupts_update(s);
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}
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break;
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case 0x28: /* I2C_OA */
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s->addr[0] = value & 0x3ff;
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break;
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case 0x2c: /* I2C_SA */
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s->addr[1] = value & 0x3ff;
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break;
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case 0x30: /* I2C_PSC */
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s->divider = value;
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break;
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case 0x34: /* I2C_SCLL */
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s->times[0] = value;
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break;
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case 0x38: /* I2C_SCLH */
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s->times[1] = value;
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break;
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case 0x3c: /* I2C_SYSTEST */
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s->test = value & 0xf80f;
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if (value & (1 << 11)) /* SBB */
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if (s->revision >= OMAP2_INTR_REV) {
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s->stat |= 0x3f;
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omap_i2c_interrupts_update(s);
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}
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if (value & (1 << 15)) /* ST_EN */
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fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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}
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s->fifo <<= 8;
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s->txlen += 1;
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s->fifo |= value & 0xff;
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc *omap_i2c_readfn[] = {
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omap_badwidth_read16,
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omap_i2c_read,
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omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
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omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
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omap_i2c_write,
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omap_badwidth_write16,
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};
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struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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qemu_irq irq, qemu_irq *dma, omap_clk clk)
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{
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int iomemtype;
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struct omap_i2c_s *s = (struct omap_i2c_s *)
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qemu_mallocz(sizeof(struct omap_i2c_s));
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/* TODO: set a value greater or equal to real hardware */
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s->revision = 0x11;
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s->irq = irq;
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s->drq[0] = dma[0];
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s->drq[1] = dma[1];
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s->bus = i2c_init_bus(NULL, "i2c");
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omap_i2c_reset(s);
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iomemtype = cpu_register_io_memory(omap_i2c_readfn,
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omap_i2c_writefn, s);
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cpu_register_physical_memory(base, 0x800, iomemtype);
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return s;
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}
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struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
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qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
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{
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int iomemtype;
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struct omap_i2c_s *s = (struct omap_i2c_s *)
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qemu_mallocz(sizeof(struct omap_i2c_s));
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s->revision = 0x34;
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s->irq = irq;
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s->drq[0] = dma[0];
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s->drq[1] = dma[1];
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s->bus = i2c_init_bus(NULL, "i2c");
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omap_i2c_reset(s);
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iomemtype = l4_register_io_memory(omap_i2c_readfn,
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omap_i2c_writefn, s);
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omap_l4_attach(ta, 0, iomemtype);
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return s;
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}
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i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
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{
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return s->bus;
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}
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