419 lines
11 KiB
C
419 lines
11 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright IBM Corp. 2008
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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/* This file implements emulation of the 32-bit PCI controller found in some
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* 4xx SoCs, such as the 440EP. */
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#include "hw.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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typedef target_phys_addr_t pci_addr_t;
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#include "pci.h"
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#include "pci_host.h"
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#include "bswap.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif /* DEBUG */
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struct PCIMasterMap {
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uint32_t la;
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uint32_t ma;
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uint32_t pcila;
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uint32_t pciha;
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};
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struct PCITargetMap {
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uint32_t ms;
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uint32_t la;
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};
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#define PPC4xx_PCI_NR_PMMS 3
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#define PPC4xx_PCI_NR_PTMS 2
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struct PPC4xxPCIState {
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struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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PCIHostState pci_state;
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PCIDevice *pci_dev;
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};
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typedef struct PPC4xxPCIState PPC4xxPCIState;
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#define PCIC0_CFGADDR 0x0
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#define PCIC0_CFGDATA 0x4
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/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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* PCI accesses. */
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#define PCIL0_PMM0LA 0x0
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#define PCIL0_PMM0MA 0x4
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#define PCIL0_PMM0PCILA 0x8
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#define PCIL0_PMM0PCIHA 0xc
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#define PCIL0_PMM1LA 0x10
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#define PCIL0_PMM1MA 0x14
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#define PCIL0_PMM1PCILA 0x18
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#define PCIL0_PMM1PCIHA 0x1c
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#define PCIL0_PMM2LA 0x20
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#define PCIL0_PMM2MA 0x24
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#define PCIL0_PMM2PCILA 0x28
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#define PCIL0_PMM2PCIHA 0x2c
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/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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* PLB accesses. */
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#define PCIL0_PTM1MS 0x30
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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#define PCI_REG_SIZE 0x40
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static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
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{
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PPC4xxPCIState *ppc4xx_pci = opaque;
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return ppc4xx_pci->pci_state.config_reg;
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}
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static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
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&pci4xx_cfgaddr_readl,
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&pci4xx_cfgaddr_readl,
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&pci4xx_cfgaddr_readl,
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};
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static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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PPC4xxPCIState *ppc4xx_pci = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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ppc4xx_pci->pci_state.config_reg = value & ~0x3;
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}
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static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
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&pci4xx_cfgaddr_writel,
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&pci4xx_cfgaddr_writel,
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&pci4xx_cfgaddr_writel,
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};
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static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
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&pci_host_data_readb,
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&pci_host_data_readw,
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&pci_host_data_readl,
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};
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static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
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&pci_host_data_writeb,
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&pci_host_data_writew,
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&pci_host_data_writel,
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};
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static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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struct PPC4xxPCIState *pci = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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/* We ignore all target attempts at PCI configuration, effectively
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* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
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switch (offset) {
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case PCIL0_PMM0LA:
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pci->pmm[0].la = value;
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break;
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case PCIL0_PMM0MA:
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pci->pmm[0].ma = value;
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break;
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case PCIL0_PMM0PCIHA:
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pci->pmm[0].pciha = value;
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break;
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case PCIL0_PMM0PCILA:
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pci->pmm[0].pcila = value;
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break;
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case PCIL0_PMM1LA:
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pci->pmm[1].la = value;
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break;
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case PCIL0_PMM1MA:
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pci->pmm[1].ma = value;
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break;
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case PCIL0_PMM1PCIHA:
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pci->pmm[1].pciha = value;
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break;
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case PCIL0_PMM1PCILA:
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pci->pmm[1].pcila = value;
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break;
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case PCIL0_PMM2LA:
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pci->pmm[2].la = value;
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break;
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case PCIL0_PMM2MA:
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pci->pmm[2].ma = value;
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break;
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case PCIL0_PMM2PCIHA:
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pci->pmm[2].pciha = value;
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break;
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case PCIL0_PMM2PCILA:
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pci->pmm[2].pcila = value;
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break;
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case PCIL0_PTM1MS:
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pci->ptm[0].ms = value;
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break;
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case PCIL0_PTM1LA:
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pci->ptm[0].la = value;
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break;
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case PCIL0_PTM2MS:
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pci->ptm[1].ms = value;
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break;
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case PCIL0_PTM2LA:
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pci->ptm[1].la = value;
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break;
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default:
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printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
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(unsigned long)offset);
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break;
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}
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}
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static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
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{
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struct PPC4xxPCIState *pci = opaque;
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uint32_t value;
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switch (offset) {
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case PCIL0_PMM0LA:
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value = pci->pmm[0].la;
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break;
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case PCIL0_PMM0MA:
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value = pci->pmm[0].ma;
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break;
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case PCIL0_PMM0PCIHA:
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value = pci->pmm[0].pciha;
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break;
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case PCIL0_PMM0PCILA:
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value = pci->pmm[0].pcila;
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break;
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case PCIL0_PMM1LA:
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value = pci->pmm[1].la;
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break;
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case PCIL0_PMM1MA:
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value = pci->pmm[1].ma;
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break;
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case PCIL0_PMM1PCIHA:
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value = pci->pmm[1].pciha;
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break;
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case PCIL0_PMM1PCILA:
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value = pci->pmm[1].pcila;
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break;
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case PCIL0_PMM2LA:
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value = pci->pmm[2].la;
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break;
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case PCIL0_PMM2MA:
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value = pci->pmm[2].ma;
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break;
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case PCIL0_PMM2PCIHA:
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value = pci->pmm[2].pciha;
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break;
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case PCIL0_PMM2PCILA:
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value = pci->pmm[2].pcila;
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break;
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case PCIL0_PTM1MS:
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value = pci->ptm[0].ms;
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break;
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case PCIL0_PTM1LA:
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value = pci->ptm[0].la;
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break;
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case PCIL0_PTM2MS:
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value = pci->ptm[1].ms;
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break;
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case PCIL0_PTM2LA:
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value = pci->ptm[1].la;
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break;
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default:
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printf("%s: invalid PCI internal register 0x%lx\n", __func__,
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(unsigned long)offset);
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value = 0;
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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return value;
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}
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static CPUReadMemoryFunc *pci_reg_read[] = {
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&ppc4xx_pci_reg_read4,
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&ppc4xx_pci_reg_read4,
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&ppc4xx_pci_reg_read4,
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};
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static CPUWriteMemoryFunc *pci_reg_write[] = {
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&ppc4xx_pci_reg_write4,
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&ppc4xx_pci_reg_write4,
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&ppc4xx_pci_reg_write4,
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};
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static void ppc4xx_pci_reset(void *opaque)
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{
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struct PPC4xxPCIState *pci = opaque;
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memset(pci->pmm, 0, sizeof(pci->pmm));
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memset(pci->ptm, 0, sizeof(pci->ptm));
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}
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/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
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* may need further refactoring for other boards. */
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static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int slot = pci_dev->devfn >> 3;
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DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
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pci_dev->devfn, irq_num, slot);
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return slot - 1;
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}
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static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level)
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{
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DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
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qemu_set_irq(pci_irqs[irq_num], level);
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}
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static void ppc4xx_pci_save(QEMUFile *f, void *opaque)
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{
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PPC4xxPCIState *controller = opaque;
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int i;
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pci_device_save(controller->pci_dev, f);
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for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
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qemu_put_be32s(f, &controller->pmm[i].la);
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qemu_put_be32s(f, &controller->pmm[i].ma);
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qemu_put_be32s(f, &controller->pmm[i].pcila);
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qemu_put_be32s(f, &controller->pmm[i].pciha);
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}
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for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
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qemu_put_be32s(f, &controller->ptm[i].ms);
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qemu_put_be32s(f, &controller->ptm[i].la);
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}
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}
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static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id)
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{
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PPC4xxPCIState *controller = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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pci_device_load(controller->pci_dev, f);
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for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
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qemu_get_be32s(f, &controller->pmm[i].la);
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qemu_get_be32s(f, &controller->pmm[i].ma);
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qemu_get_be32s(f, &controller->pmm[i].pcila);
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qemu_get_be32s(f, &controller->pmm[i].pciha);
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}
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for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
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qemu_get_be32s(f, &controller->ptm[i].ms);
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qemu_get_be32s(f, &controller->ptm[i].la);
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}
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return 0;
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}
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/* XXX Interrupt acknowledge cycles not supported. */
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PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers)
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{
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PPC4xxPCIState *controller;
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int index;
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static int ppc4xx_pci_id;
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uint8_t *pci_conf;
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controller = qemu_mallocz(sizeof(PPC4xxPCIState));
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controller->pci_state.bus = pci_register_bus(NULL, "pci",
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ppc4xx_pci_set_irq,
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ppc4xx_pci_map_irq,
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pci_irqs, 0, 4);
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controller->pci_dev = pci_register_device(controller->pci_state.bus,
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"host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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pci_conf = controller->pci_dev->config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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/* CFGADDR */
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index = cpu_register_io_memory(pci4xx_cfgaddr_read,
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pci4xx_cfgaddr_write, controller);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
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/* CFGDATA */
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index = cpu_register_io_memory(pci4xx_cfgdata_read,
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pci4xx_cfgdata_write,
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&controller->pci_state);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
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/* Internal registers */
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index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
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qemu_register_reset(ppc4xx_pci_reset, controller);
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/* XXX load/save code not tested. */
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register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
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ppc4xx_pci_save, ppc4xx_pci_load, controller);
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return controller->pci_state.bus;
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free:
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printf("%s error\n", __func__);
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qemu_free(controller);
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return NULL;
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}
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