638b752da3
An initial simple upstream port emulation to allow the creation of CXL switches. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-2-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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.. | ||
cxl_root_port.c | ||
cxl_upstream.c | ||
dec.c | ||
dec.h | ||
gen_pcie_root_port.c | ||
i82801b11.c | ||
ioh3420.c | ||
Kconfig | ||
meson.build | ||
pci_bridge_dev.c | ||
pci_expander_bridge_stubs.c | ||
pci_expander_bridge.c | ||
pcie_pci_bridge.c | ||
pcie_root_port.c | ||
simba.c | ||
xio3130_downstream.c | ||
xio3130_upstream.c |