519 lines
14 KiB
C
519 lines
14 KiB
C
/*
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* Intel XScale PXA255/270 OS Timers.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2006 Thorsten Zitterell
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "pxa.h"
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#include "sysbus.h"
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#define OSMR0 0x00
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#define OSMR1 0x04
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#define OSMR2 0x08
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#define OSMR3 0x0c
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#define OSMR4 0x80
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#define OSMR5 0x84
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#define OSMR6 0x88
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#define OSMR7 0x8c
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#define OSMR8 0x90
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#define OSMR9 0x94
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#define OSMR10 0x98
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#define OSMR11 0x9c
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#define OSCR 0x10 /* OS Timer Count */
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#define OSCR4 0x40
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#define OSCR5 0x44
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#define OSCR6 0x48
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#define OSCR7 0x4c
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#define OSCR8 0x50
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#define OSCR9 0x54
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#define OSCR10 0x58
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#define OSCR11 0x5c
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#define OSSR 0x14 /* Timer status register */
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#define OWER 0x18
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#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
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#define OMCR4 0xc0 /* OS Match Control registers */
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#define OMCR5 0xc4
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#define OMCR6 0xc8
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#define OMCR7 0xcc
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#define OMCR8 0xd0
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#define OMCR9 0xd4
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#define OMCR10 0xd8
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#define OMCR11 0xdc
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#define OSNR 0x20
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#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
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#define PXA27X_FREQ 3250000 /* 3.25 MHz */
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static int pxa2xx_timer4_freq[8] = {
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[0] = 0,
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[1] = 32768,
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[2] = 1000,
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[3] = 1,
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[4] = 1000000,
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/* [5] is the "Externally supplied clock". Assign if necessary. */
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[5 ... 7] = 0,
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};
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typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
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typedef struct {
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uint32_t value;
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qemu_irq irq;
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QEMUTimer *qtimer;
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int num;
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PXA2xxTimerInfo *info;
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} PXA2xxTimer0;
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typedef struct {
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PXA2xxTimer0 tm;
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int32_t oldclock;
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int32_t clock;
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uint64_t lastload;
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uint32_t freq;
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uint32_t control;
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} PXA2xxTimer4;
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struct PXA2xxTimerInfo {
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SysBusDevice busdev;
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uint32_t flags;
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int32_t clock;
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int32_t oldclock;
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uint64_t lastload;
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uint32_t freq;
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PXA2xxTimer0 timer[4];
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uint32_t events;
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uint32_t irq_enabled;
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uint32_t reset3;
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uint32_t snapshot;
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qemu_irq irq4;
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PXA2xxTimer4 tm4[8];
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};
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#define PXA2XX_TIMER_HAVE_TM4 0
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static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
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{
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return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
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}
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int i;
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uint32_t now_vm;
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uint64_t new_qemu;
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now_vm = s->clock +
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muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
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for (i = 0; i < 4; i ++) {
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new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
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get_ticks_per_sec(), s->freq);
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qemu_mod_timer(s->timer[i].qtimer, new_qemu);
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}
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}
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static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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uint32_t now_vm;
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uint64_t new_qemu;
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
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int counter;
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if (s->tm4[n].control & (1 << 7))
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counter = n;
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else
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counter = counters[n];
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if (!s->tm4[counter].freq) {
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qemu_del_timer(s->tm4[n].tm.qtimer);
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return;
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}
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now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
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s->tm4[counter].lastload,
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s->tm4[counter].freq, get_ticks_per_sec());
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new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
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get_ticks_per_sec(), s->tm4[counter].freq);
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qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
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}
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static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int tm = 0;
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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return s->timer[tm].value;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].tm.value;
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case OSCR:
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return s->clock + muldiv64(qemu_get_clock(vm_clock) -
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s->lastload, s->freq, get_ticks_per_sec());
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
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if (s->tm4[tm - 1].freq)
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s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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qemu_get_clock(vm_clock) -
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s->tm4[tm - 1].lastload,
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s->tm4[tm - 1].freq, get_ticks_per_sec());
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else
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s->snapshot = s->tm4[tm - 1].clock;
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}
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if (!s->tm4[tm].freq)
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return s->tm4[tm].clock;
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return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
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s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
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case OIER:
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return s->irq_enabled;
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case OSSR: /* Status register */
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return s->events;
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case OWER:
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return s->reset3;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm ++;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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return s->tm4[tm].control;
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case OSNR:
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return s->snapshot;
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default:
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badreg:
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hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
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}
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return 0;
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}
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static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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int i, tm = 0;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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s->timer[tm].value = value;
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pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
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break;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].tm.value = value;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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break;
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case OSCR:
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s->oldclock = s->clock;
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s->lastload = qemu_get_clock(vm_clock);
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s->clock = value;
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pxa2xx_timer_update(s, s->lastload);
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break;
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].oldclock = s->tm4[tm].clock;
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s->tm4[tm].lastload = qemu_get_clock(vm_clock);
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s->tm4[tm].clock = value;
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pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
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break;
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case OIER:
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s->irq_enabled = value & 0xfff;
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break;
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case OSSR: /* Status register */
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value &= s->events;
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s->events &= ~value;
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for (i = 0; i < 4; i ++, value >>= 1)
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if (value & 1)
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qemu_irq_lower(s->timer[i].irq);
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if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
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qemu_irq_lower(s->irq4);
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break;
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case OWER: /* XXX: Reset on OSMR3 match? */
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s->reset3 = value;
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break;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].control = value & 0x0ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || tm == 0)
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s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
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else {
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s->tm4[tm].freq = 0;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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}
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break;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm += 4;
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if (!pxa2xx_timer_has_tm4(s))
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goto badreg;
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s->tm4[tm].control = value & 0x3ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || !(tm & 1))
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s->tm4[tm].freq =
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pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
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else {
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s->tm4[tm].freq = 0;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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}
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break;
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default:
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badreg:
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hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
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}
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}
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static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
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pxa2xx_timer_read,
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pxa2xx_timer_read,
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pxa2xx_timer_read,
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};
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static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
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pxa2xx_timer_write,
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pxa2xx_timer_write,
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pxa2xx_timer_write,
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};
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static void pxa2xx_timer_tick(void *opaque)
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{
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PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
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PXA2xxTimerInfo *i = t->info;
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if (i->irq_enabled & (1 << t->num)) {
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i->events |= 1 << t->num;
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qemu_irq_raise(t->irq);
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}
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if (t->num == 3)
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if (i->reset3 & 1) {
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i->reset3 = 0;
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qemu_system_reset_request();
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}
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}
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static void pxa2xx_timer_tick4(void *opaque)
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{
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PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
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PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
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pxa2xx_timer_tick(&t->tm);
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if (t->control & (1 << 3))
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t->clock = 0;
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if (t->control & (1 << 6))
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pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
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if (i->events & 0xff0)
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qemu_irq_raise(i->irq4);
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}
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static int pxa25x_timer_post_load(void *opaque, int version_id)
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{
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int64_t now;
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int i;
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now = qemu_get_clock(vm_clock);
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pxa2xx_timer_update(s, now);
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if (pxa2xx_timer_has_tm4(s))
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for (i = 0; i < 8; i ++)
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pxa2xx_timer_update4(s, now, i);
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return 0;
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}
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static int pxa2xx_timer_init(SysBusDevice *dev)
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{
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int i;
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int iomemtype;
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PXA2xxTimerInfo *s;
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s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
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s->irq_enabled = 0;
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s->oldclock = 0;
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s->clock = 0;
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s->lastload = qemu_get_clock(vm_clock);
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s->reset3 = 0;
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for (i = 0; i < 4; i ++) {
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s->timer[i].value = 0;
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sysbus_init_irq(dev, &s->timer[i].irq);
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s->timer[i].info = s;
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s->timer[i].num = i;
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s->timer[i].qtimer = qemu_new_timer(vm_clock,
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pxa2xx_timer_tick, &s->timer[i]);
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}
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if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
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sysbus_init_irq(dev, &s->irq4);
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for (i = 0; i < 8; i ++) {
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s->tm4[i].tm.value = 0;
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s->tm4[i].tm.info = s;
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s->tm4[i].tm.num = i + 4;
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s->tm4[i].freq = 0;
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s->tm4[i].control = 0x0;
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s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
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pxa2xx_timer_tick4, &s->tm4[i]);
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}
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}
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iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
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pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x00001000, iomemtype);
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return 0;
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}
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static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
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.name = "pxa2xx_timer0",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(value, PXA2xxTimer0),
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VMSTATE_END_OF_LIST(),
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},
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};
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static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
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.name = "pxa2xx_timer4",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
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vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
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VMSTATE_INT32(oldclock, PXA2xxTimer4),
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VMSTATE_INT32(clock, PXA2xxTimer4),
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VMSTATE_UINT64(lastload, PXA2xxTimer4),
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VMSTATE_UINT32(freq, PXA2xxTimer4),
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VMSTATE_UINT32(control, PXA2xxTimer4),
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VMSTATE_END_OF_LIST(),
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},
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};
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static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
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{
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return pxa2xx_timer_has_tm4(opaque);
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}
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static const VMStateDescription vmstate_pxa2xx_timer_regs = {
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.name = "pxa2xx_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = pxa25x_timer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(clock, PXA2xxTimerInfo),
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VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
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VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
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VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
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vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
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VMSTATE_UINT32(events, PXA2xxTimerInfo),
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VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
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VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
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VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
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VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
|
|
pxa2xx_timer_has_tm4_test, 0,
|
|
vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
|
|
VMSTATE_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static SysBusDeviceInfo pxa25x_timer_dev_info = {
|
|
.init = pxa2xx_timer_init,
|
|
.qdev.name = "pxa25x-timer",
|
|
.qdev.desc = "PXA25x timer",
|
|
.qdev.size = sizeof(PXA2xxTimerInfo),
|
|
.qdev.vmsd = &vmstate_pxa2xx_timer_regs,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
|
|
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
|
PXA2XX_TIMER_HAVE_TM4, false),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static SysBusDeviceInfo pxa27x_timer_dev_info = {
|
|
.init = pxa2xx_timer_init,
|
|
.qdev.name = "pxa27x-timer",
|
|
.qdev.desc = "PXA27x timer",
|
|
.qdev.size = sizeof(PXA2xxTimerInfo),
|
|
.qdev.vmsd = &vmstate_pxa2xx_timer_regs,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
|
|
DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
|
PXA2XX_TIMER_HAVE_TM4, true),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static void pxa2xx_timer_register(void)
|
|
{
|
|
sysbus_register_withprop(&pxa25x_timer_dev_info);
|
|
sysbus_register_withprop(&pxa27x_timer_dev_info);
|
|
};
|
|
device_init(pxa2xx_timer_register);
|