Yongbok Kim 01bc435b44 target-mips: implement R6 multi-threading ... MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>		2016-02-26 08:59:17 +00:00
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cpu-qom.h
cpu.c	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
cpu.h	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
dsp_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
gdbstub.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
helper.c	log: do not unnecessarily include qom/cpu.h	2016-02-03 09:19:10 +00:00
helper.h	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
kvm_mips.h
kvm.c	mips/kvm: Support MSA in MIPS KVM guests	2016-02-26 08:59:17 +00:00
lmi_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
machine.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
Makefile.objs
mips-defs.h
mips-semi.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
msa_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
op_helper.c	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
TODO
translate_init.c	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
translate.c	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00