a39c1d47ac
This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and extends the IRQ routing setup by the 0->2 redirection when needed. The kvm-ioapic model has a property that allows to define its GSI base for injecting interrupts into the kernel model. This will allow to disentangle PIC and IOAPIC pins for chipsets that support more sophisticated IRQ routes than the PIIX3. So far the base is kept at 0, i.e. PIC and IOAPIC share pins 0..15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
/*
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* KVM in-kernel IOPIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/pc.h"
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#include "hw/ioapic_internal.h"
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#include "hw/apic_internal.h"
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#include "kvm.h"
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typedef struct KVMIOAPICState KVMIOAPICState;
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struct KVMIOAPICState {
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IOAPICCommonState ioapic;
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uint32_t kvm_gsi_base;
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};
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static void kvm_ioapic_get(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
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abort();
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}
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kioapic = &chip.chip.ioapic;
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s->id = kioapic->id;
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s->ioregsel = kioapic->ioregsel;
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s->irr = kioapic->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = kioapic->redirtbl[i].bits;
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}
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}
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static void kvm_ioapic_put(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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kioapic = &chip.chip.ioapic;
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kioapic->id = s->id;
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kioapic->ioregsel = s->ioregsel;
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kioapic->base_address = s->busdev.mmio[0].addr;
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kioapic->irr = s->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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kioapic->redirtbl[i].bits = s->ioredtbl[i];
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}
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ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret));
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abort();
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}
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}
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static void kvm_ioapic_reset(DeviceState *dev)
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{
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IOAPICCommonState *s = DO_UPCAST(IOAPICCommonState, busdev.qdev, dev);
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ioapic_reset_common(dev);
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kvm_ioapic_put(s);
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}
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static void kvm_ioapic_set_irq(void *opaque, int irq, int level)
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{
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KVMIOAPICState *s = opaque;
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int delivered;
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delivered = kvm_irqchip_set_irq(kvm_state, s->kvm_gsi_base + irq, level);
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apic_report_irq_delivered(delivered);
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}
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static void kvm_ioapic_init(IOAPICCommonState *s, int instance_no)
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{
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memory_region_init_reservation(&s->io_memory, "kvm-ioapic", 0x1000);
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qdev_init_gpio_in(&s->busdev.qdev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
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}
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static IOAPICCommonInfo kvm_ioapic_info = {
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.busdev.qdev.name = "kvm-ioapic",
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.busdev.qdev.size = sizeof(KVMIOAPICState),
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.busdev.qdev.reset = kvm_ioapic_reset,
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.busdev.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0),
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DEFINE_PROP_END_OF_LIST()
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},
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.init = kvm_ioapic_init,
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.pre_save = kvm_ioapic_get,
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.post_load = kvm_ioapic_put,
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};
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static void kvm_ioapic_register_device(void)
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{
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ioapic_qdev_register(&kvm_ioapic_info);
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}
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device_init(kvm_ioapic_register_device)
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