0b8fa32f55
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
315 lines
8.7 KiB
C
315 lines
8.7 KiB
C
/*
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* Arm PrimeCell PL022 Synchronous Serial Port
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/ssi/pl022.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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//#define DEBUG_PL022 1
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#ifdef DEBUG_PL022
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#define DPRINTF(fmt, ...) \
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do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
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#endif
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#define PL022_CR1_LBM 0x01
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#define PL022_CR1_SSE 0x02
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#define PL022_CR1_MS 0x04
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#define PL022_CR1_SDO 0x08
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#define PL022_SR_TFE 0x01
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#define PL022_SR_TNF 0x02
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#define PL022_SR_RNE 0x04
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#define PL022_SR_RFF 0x08
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#define PL022_SR_BSY 0x10
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#define PL022_INT_ROR 0x01
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#define PL022_INT_RT 0x02
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#define PL022_INT_RX 0x04
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#define PL022_INT_TX 0x08
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static const unsigned char pl022_id[8] =
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{ 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static void pl022_update(PL022State *s)
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{
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s->sr = 0;
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if (s->tx_fifo_len == 0)
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s->sr |= PL022_SR_TFE;
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if (s->tx_fifo_len != 8)
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s->sr |= PL022_SR_TNF;
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if (s->rx_fifo_len != 0)
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s->sr |= PL022_SR_RNE;
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if (s->rx_fifo_len == 8)
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s->sr |= PL022_SR_RFF;
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if (s->tx_fifo_len)
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s->sr |= PL022_SR_BSY;
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s->is = 0;
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if (s->rx_fifo_len >= 4)
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s->is |= PL022_INT_RX;
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if (s->tx_fifo_len <= 4)
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s->is |= PL022_INT_TX;
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qemu_set_irq(s->irq, (s->is & s->im) != 0);
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}
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static void pl022_xfer(PL022State *s)
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{
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int i;
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int o;
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int val;
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if ((s->cr1 & PL022_CR1_SSE) == 0) {
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pl022_update(s);
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DPRINTF("Disabled\n");
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return;
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}
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DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
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i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
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o = s->rx_fifo_head;
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/* ??? We do not emulate the line speed.
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This may break some applications. The are two problematic cases:
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(a) A driver feeds data into the TX FIFO until it is full,
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and only then drains the RX FIFO. On real hardware the CPU can
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feed data fast enough that the RX fifo never gets chance to overflow.
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(b) A driver transmits data, deliberately allowing the RX FIFO to
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overflow because it ignores the RX data anyway.
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We choose to support (a) by stalling the transmit engine if it would
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cause the RX FIFO to overflow. In practice much transmit-only code
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falls into (a) because it flushes the RX FIFO to determine when
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the transfer has completed. */
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while (s->tx_fifo_len && s->rx_fifo_len < 8) {
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DPRINTF("xfer\n");
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val = s->tx_fifo[i];
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if (s->cr1 & PL022_CR1_LBM) {
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/* Loopback mode. */
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} else {
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val = ssi_transfer(s->ssi, val);
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}
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s->rx_fifo[o] = val & s->bitmask;
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i = (i + 1) & 7;
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o = (o + 1) & 7;
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s->tx_fifo_len--;
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s->rx_fifo_len++;
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}
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s->rx_fifo_head = o;
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pl022_update(s);
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}
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static uint64_t pl022_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PL022State *s = (PL022State *)opaque;
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int val;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return pl022_id[(offset - 0xfe0) >> 2];
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}
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switch (offset) {
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case 0x00: /* CR0 */
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return s->cr0;
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case 0x04: /* CR1 */
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return s->cr1;
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case 0x08: /* DR */
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if (s->rx_fifo_len) {
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val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
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DPRINTF("RX %02x\n", val);
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s->rx_fifo_len--;
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pl022_xfer(s);
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} else {
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val = 0;
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}
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return val;
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case 0x0c: /* SR */
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return s->sr;
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case 0x10: /* CPSR */
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return s->cpsr;
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case 0x14: /* IMSC */
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return s->im;
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case 0x18: /* RIS */
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return s->is;
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case 0x1c: /* MIS */
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return s->im & s->is;
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case 0x24: /* DMACR */
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/* Not implemented. */
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl022_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl022_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PL022State *s = (PL022State *)opaque;
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switch (offset) {
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case 0x00: /* CR0 */
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s->cr0 = value;
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/* Clock rate and format are ignored. */
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s->bitmask = (1 << ((value & 15) + 1)) - 1;
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break;
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case 0x04: /* CR1 */
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s->cr1 = value;
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if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
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== (PL022_CR1_MS | PL022_CR1_SSE)) {
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BADF("SPI slave mode not implemented\n");
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}
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pl022_xfer(s);
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break;
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case 0x08: /* DR */
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if (s->tx_fifo_len < 8) {
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DPRINTF("TX %02x\n", (unsigned)value);
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s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
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s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
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s->tx_fifo_len++;
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pl022_xfer(s);
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}
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break;
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case 0x10: /* CPSR */
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/* Prescaler. Ignored. */
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s->cpsr = value & 0xff;
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break;
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case 0x14: /* IMSC */
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s->im = value;
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pl022_update(s);
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break;
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case 0x20: /* ICR */
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/*
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* write-1-to-clear: bit 0 clears ROR, bit 1 clears RT;
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* RX and TX interrupts cannot be cleared this way.
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*/
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value &= PL022_INT_ROR | PL022_INT_RT;
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s->is &= ~value;
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break;
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case 0x24: /* DMACR */
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if (value) {
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qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl022_write: Bad offset %x\n", (int)offset);
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}
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}
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static void pl022_reset(DeviceState *dev)
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{
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PL022State *s = PL022(dev);
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s->rx_fifo_len = 0;
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s->tx_fifo_len = 0;
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s->im = 0;
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s->is = PL022_INT_TX;
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s->sr = PL022_SR_TFE | PL022_SR_TNF;
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}
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static const MemoryRegionOps pl022_ops = {
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.read = pl022_read,
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.write = pl022_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pl022_post_load(void *opaque, int version_id)
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{
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PL022State *s = opaque;
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if (s->tx_fifo_head < 0 ||
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s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) ||
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s->rx_fifo_head < 0 ||
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s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
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return -1;
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}
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return 0;
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}
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static const VMStateDescription vmstate_pl022 = {
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.name = "pl022_ssp",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pl022_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr0, PL022State),
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VMSTATE_UINT32(cr1, PL022State),
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VMSTATE_UINT32(bitmask, PL022State),
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VMSTATE_UINT32(sr, PL022State),
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VMSTATE_UINT32(cpsr, PL022State),
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VMSTATE_UINT32(is, PL022State),
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VMSTATE_UINT32(im, PL022State),
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VMSTATE_INT32(tx_fifo_head, PL022State),
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VMSTATE_INT32(rx_fifo_head, PL022State),
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VMSTATE_INT32(tx_fifo_len, PL022State),
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VMSTATE_INT32(rx_fifo_len, PL022State),
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VMSTATE_UINT16(tx_fifo[0], PL022State),
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VMSTATE_UINT16(rx_fifo[0], PL022State),
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VMSTATE_UINT16(tx_fifo[1], PL022State),
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VMSTATE_UINT16(rx_fifo[1], PL022State),
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VMSTATE_UINT16(tx_fifo[2], PL022State),
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VMSTATE_UINT16(rx_fifo[2], PL022State),
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VMSTATE_UINT16(tx_fifo[3], PL022State),
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VMSTATE_UINT16(rx_fifo[3], PL022State),
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VMSTATE_UINT16(tx_fifo[4], PL022State),
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VMSTATE_UINT16(rx_fifo[4], PL022State),
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VMSTATE_UINT16(tx_fifo[5], PL022State),
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VMSTATE_UINT16(rx_fifo[5], PL022State),
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VMSTATE_UINT16(tx_fifo[6], PL022State),
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VMSTATE_UINT16(rx_fifo[6], PL022State),
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VMSTATE_UINT16(tx_fifo[7], PL022State),
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VMSTATE_UINT16(rx_fifo[7], PL022State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pl022_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PL022State *s = PL022(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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s->ssi = ssi_create_bus(dev, "ssi");
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}
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static void pl022_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pl022_reset;
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dc->vmsd = &vmstate_pl022;
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dc->realize = pl022_realize;
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}
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static const TypeInfo pl022_info = {
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.name = TYPE_PL022,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PL022State),
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.class_init = pl022_class_init,
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};
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static void pl022_register_types(void)
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{
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type_register_static(&pl022_info);
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}
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type_init(pl022_register_types)
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