650d103d3e
In my "build everything" tree, changing hw/hw.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The previous commits have left only the declaration of hw_error() in hw/hw.h. This permits dropping most of its inclusions. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-19-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
374 lines
11 KiB
C
374 lines
11 KiB
C
/*
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* PPC4xx I2C controller emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "cpu.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "hw/irq.h"
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#define PPC4xx_I2C_MEM_SIZE 18
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enum {
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IIC_MDBUF = 0,
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/* IIC_SDBUF = 2, */
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IIC_LMADR = 4,
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IIC_HMADR,
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IIC_CNTL,
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IIC_MDCNTL,
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IIC_STS,
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IIC_EXTSTS,
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IIC_LSADR,
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IIC_HSADR,
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IIC_CLKDIV,
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IIC_INTRMSK,
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IIC_XFRCNT,
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IIC_XTCNTLSS,
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IIC_DIRECTCNTL
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/* IIC_INTR */
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};
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#define IIC_CNTL_PT (1 << 0)
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#define IIC_CNTL_READ (1 << 1)
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#define IIC_CNTL_CHT (1 << 2)
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#define IIC_CNTL_RPST (1 << 3)
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#define IIC_CNTL_AMD (1 << 6)
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#define IIC_CNTL_HMT (1 << 7)
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#define IIC_MDCNTL_EINT (1 << 2)
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#define IIC_MDCNTL_ESM (1 << 3)
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#define IIC_MDCNTL_FMDB (1 << 6)
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#define IIC_STS_PT (1 << 0)
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#define IIC_STS_IRQA (1 << 1)
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#define IIC_STS_ERR (1 << 2)
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#define IIC_STS_MDBF (1 << 4)
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#define IIC_STS_MDBS (1 << 5)
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#define IIC_EXTSTS_XFRA (1 << 0)
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#define IIC_EXTSTS_BCS_FREE (4 << 4)
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#define IIC_EXTSTS_BCS_BUSY (5 << 4)
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#define IIC_INTRMSK_EIMTC (1 << 0)
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#define IIC_INTRMSK_EITA (1 << 1)
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#define IIC_INTRMSK_EIIC (1 << 2)
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#define IIC_INTRMSK_EIHE (1 << 3)
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#define IIC_XTCNTLSS_SRST (1 << 0)
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#define IIC_DIRECTCNTL_SDAC (1 << 3)
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#define IIC_DIRECTCNTL_SCLC (1 << 2)
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#define IIC_DIRECTCNTL_MSDA (1 << 1)
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#define IIC_DIRECTCNTL_MSCL (1 << 0)
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static void ppc4xx_i2c_reset(DeviceState *s)
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{
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PPC4xxI2CState *i2c = PPC4xx_I2C(s);
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i2c->mdidx = -1;
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memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));
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/* [hl][ms]addr are not affected by reset */
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i2c->cntl = 0;
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i2c->mdcntl = 0;
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i2c->sts = 0;
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i2c->extsts = IIC_EXTSTS_BCS_FREE;
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i2c->clkdiv = 0;
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i2c->intrmsk = 0;
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i2c->xfrcnt = 0;
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i2c->xtcntlss = 0;
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i2c->directcntl = 0xf; /* all non-reserved bits set */
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}
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static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
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{
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PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
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uint64_t ret;
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int i;
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switch (addr) {
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case IIC_MDBUF:
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if (i2c->mdidx < 0) {
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ret = 0xff;
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break;
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}
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ret = i2c->mdata[0];
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if (i2c->mdidx == 3) {
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i2c->sts &= ~IIC_STS_MDBF;
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} else if (i2c->mdidx == 0) {
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i2c->sts &= ~IIC_STS_MDBS;
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}
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for (i = 0; i < i2c->mdidx; i++) {
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i2c->mdata[i] = i2c->mdata[i + 1];
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}
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if (i2c->mdidx >= 0) {
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i2c->mdidx--;
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}
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break;
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case IIC_LMADR:
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ret = i2c->lmadr;
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break;
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case IIC_HMADR:
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ret = i2c->hmadr;
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break;
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case IIC_CNTL:
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ret = i2c->cntl;
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break;
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case IIC_MDCNTL:
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ret = i2c->mdcntl;
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break;
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case IIC_STS:
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ret = i2c->sts;
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break;
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case IIC_EXTSTS:
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ret = i2c_bus_busy(i2c->bus) ?
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IIC_EXTSTS_BCS_BUSY : IIC_EXTSTS_BCS_FREE;
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break;
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case IIC_LSADR:
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ret = i2c->lsadr;
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break;
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case IIC_HSADR:
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ret = i2c->hsadr;
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break;
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case IIC_CLKDIV:
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ret = i2c->clkdiv;
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break;
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case IIC_INTRMSK:
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ret = i2c->intrmsk;
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break;
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case IIC_XFRCNT:
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ret = i2c->xfrcnt;
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break;
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case IIC_XTCNTLSS:
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ret = i2c->xtcntlss;
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break;
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case IIC_DIRECTCNTL:
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ret = i2c->directcntl;
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break;
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default:
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if (addr < PPC4xx_I2C_MEM_SIZE) {
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qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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}
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ret = 0;
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break;
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}
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return ret;
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}
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static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
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unsigned int size)
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{
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PPC4xxI2CState *i2c = opaque;
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switch (addr) {
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case IIC_MDBUF:
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if (i2c->mdidx >= 3) {
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break;
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}
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i2c->mdata[++i2c->mdidx] = value;
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if (i2c->mdidx == 3) {
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i2c->sts |= IIC_STS_MDBF;
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} else if (i2c->mdidx == 0) {
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i2c->sts |= IIC_STS_MDBS;
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}
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break;
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case IIC_LMADR:
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i2c->lmadr = value;
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break;
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case IIC_HMADR:
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i2c->hmadr = value;
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break;
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case IIC_CNTL:
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i2c->cntl = value & ~IIC_CNTL_PT;
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if (value & IIC_CNTL_AMD) {
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qemu_log_mask(LOG_UNIMP, "%s: only 7 bit addresses supported\n",
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__func__);
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}
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if (value & IIC_CNTL_HMT && i2c_bus_busy(i2c->bus)) {
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i2c_end_transfer(i2c->bus);
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if (i2c->mdcntl & IIC_MDCNTL_EINT &&
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i2c->intrmsk & IIC_INTRMSK_EIHE) {
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i2c->sts |= IIC_STS_IRQA;
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qemu_irq_raise(i2c->irq);
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}
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} else if (value & IIC_CNTL_PT) {
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int recv = (value & IIC_CNTL_READ) >> 1;
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int tct = value >> 4 & 3;
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int i;
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if (recv && (i2c->lmadr >> 1) >= 0x50 && (i2c->lmadr >> 1) < 0x58) {
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/* smbus emulation does not like multi byte reads w/o restart */
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value |= IIC_CNTL_RPST;
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}
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for (i = 0; i <= tct; i++) {
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if (!i2c_bus_busy(i2c->bus)) {
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i2c->extsts = IIC_EXTSTS_BCS_FREE;
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if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, recv)) {
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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break;
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} else {
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i2c->sts &= ~IIC_STS_ERR;
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}
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}
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if (!(i2c->sts & IIC_STS_ERR) &&
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i2c_send_recv(i2c->bus, &i2c->mdata[i], !recv)) {
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i2c->sts |= IIC_STS_ERR;
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i2c->extsts |= IIC_EXTSTS_XFRA;
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break;
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}
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if (value & IIC_CNTL_RPST || !(value & IIC_CNTL_CHT)) {
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i2c_end_transfer(i2c->bus);
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}
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}
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i2c->xfrcnt = i;
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i2c->mdidx = i - 1;
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if (recv && i2c->mdidx >= 0) {
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i2c->sts |= IIC_STS_MDBS;
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}
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if (recv && i2c->mdidx == 3) {
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i2c->sts |= IIC_STS_MDBF;
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}
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if (i && i2c->mdcntl & IIC_MDCNTL_EINT &&
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i2c->intrmsk & IIC_INTRMSK_EIMTC) {
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i2c->sts |= IIC_STS_IRQA;
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qemu_irq_raise(i2c->irq);
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}
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}
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break;
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case IIC_MDCNTL:
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i2c->mdcntl = value & 0x3d;
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if (value & IIC_MDCNTL_ESM) {
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qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
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__func__);
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}
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if (value & IIC_MDCNTL_FMDB) {
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i2c->mdidx = -1;
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memset(i2c->mdata, 0, ARRAY_SIZE(i2c->mdata));
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i2c->sts &= ~(IIC_STS_MDBF | IIC_STS_MDBS);
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}
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break;
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case IIC_STS:
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i2c->sts &= ~(value & 0x0a);
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if (value & IIC_STS_IRQA && i2c->mdcntl & IIC_MDCNTL_EINT) {
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qemu_irq_lower(i2c->irq);
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}
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break;
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case IIC_EXTSTS:
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i2c->extsts &= ~(value & 0x8f);
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break;
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case IIC_LSADR:
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i2c->lsadr = value;
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break;
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case IIC_HSADR:
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i2c->hsadr = value;
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break;
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case IIC_CLKDIV:
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i2c->clkdiv = value;
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break;
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case IIC_INTRMSK:
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i2c->intrmsk = value;
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break;
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case IIC_XFRCNT:
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i2c->xfrcnt = value & 0x77;
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break;
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case IIC_XTCNTLSS:
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i2c->xtcntlss &= ~(value & 0xf0);
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if (value & IIC_XTCNTLSS_SRST) {
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/* Is it actually a full reset? U-Boot sets some regs before */
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ppc4xx_i2c_reset(DEVICE(i2c));
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break;
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}
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break;
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case IIC_DIRECTCNTL:
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i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);
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i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);
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bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SCL,
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i2c->directcntl & IIC_DIRECTCNTL_MSCL);
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i2c->directcntl |= bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SDA,
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(value & IIC_DIRECTCNTL_SDAC) != 0) << 1;
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break;
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default:
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if (addr < PPC4xx_I2C_MEM_SIZE) {
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qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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}
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break;
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}
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}
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static const MemoryRegionOps ppc4xx_i2c_ops = {
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.read = ppc4xx_i2c_readb,
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.write = ppc4xx_i2c_writeb,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc4xx_i2c_init(Object *o)
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{
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PPC4xxI2CState *s = PPC4xx_I2C(o);
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memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
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TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
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s->bus = i2c_init_bus(DEVICE(s), "i2c");
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bitbang_i2c_init(&s->bitbang, s->bus);
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}
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static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ppc4xx_i2c_reset;
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}
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static const TypeInfo ppc4xx_i2c_type_info = {
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.name = TYPE_PPC4xx_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PPC4xxI2CState),
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.instance_init = ppc4xx_i2c_init,
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.class_init = ppc4xx_i2c_class_init,
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};
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static void ppc4xx_i2c_register_types(void)
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{
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type_register_static(&ppc4xx_i2c_type_info);
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}
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type_init(ppc4xx_i2c_register_types)
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