fef06c8b1b
The Clock Control Unit is responsible for clock signal generation, configuration and distribution in the Allwinner H3 System on Chip. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
243 lines
9.0 KiB
C
243 lines
9.0 KiB
C
/*
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* Allwinner H3 Clock Control Unit emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/allwinner-h3-ccu.h"
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/* CCU register offsets */
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enum {
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REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
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REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
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REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
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REG_PLL_VE = 0x0018, /* PLL VE Control */
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REG_PLL_DDR = 0x0020, /* PLL DDR Control */
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REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
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REG_PLL_GPU = 0x0038, /* PLL GPU Control */
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REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
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REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
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REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
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REG_APB1 = 0x0054, /* ARM Peripheral Bus 1 Config */
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REG_APB2 = 0x0058, /* ARM Peripheral Bus 2 Config */
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REG_DRAM_CFG = 0x00F4, /* DRAM Configuration */
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REG_MBUS = 0x00FC, /* MBUS Reset */
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REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
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REG_PLL_TIME1 = 0x0204, /* PLL Stable Time 1 */
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REG_PLL_CPUX_BIAS = 0x0220, /* PLL CPUX Bias */
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REG_PLL_AUDIO_BIAS = 0x0224, /* PLL Audio Bias */
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REG_PLL_VIDEO_BIAS = 0x0228, /* PLL Video Bias */
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REG_PLL_VE_BIAS = 0x022C, /* PLL VE Bias */
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REG_PLL_DDR_BIAS = 0x0230, /* PLL DDR Bias */
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REG_PLL_PERIPH0_BIAS = 0x0234, /* PLL Peripherals 0 Bias */
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REG_PLL_GPU_BIAS = 0x023C, /* PLL GPU Bias */
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REG_PLL_PERIPH1_BIAS = 0x0244, /* PLL Peripherals 1 Bias */
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REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
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REG_PLL_CPUX_TUNING = 0x0250, /* PLL CPUX Tuning */
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REG_PLL_DDR_TUNING = 0x0260, /* PLL DDR Tuning */
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};
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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/* CCU register flags */
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enum {
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REG_DRAM_CFG_UPDATE = (1 << 16),
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};
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enum {
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REG_PLL_ENABLE = (1 << 31),
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REG_PLL_LOCK = (1 << 28),
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};
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/* CCU register reset values */
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enum {
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REG_PLL_CPUX_RST = 0x00001000,
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REG_PLL_AUDIO_RST = 0x00035514,
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REG_PLL_VIDEO_RST = 0x03006207,
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REG_PLL_VE_RST = 0x03006207,
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REG_PLL_DDR_RST = 0x00001000,
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REG_PLL_PERIPH0_RST = 0x00041811,
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REG_PLL_GPU_RST = 0x03006207,
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REG_PLL_PERIPH1_RST = 0x00041811,
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REG_PLL_DE_RST = 0x03006207,
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REG_CPUX_AXI_RST = 0x00010000,
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REG_APB1_RST = 0x00001010,
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REG_APB2_RST = 0x01000000,
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REG_DRAM_CFG_RST = 0x00000000,
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REG_MBUS_RST = 0x80000000,
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REG_PLL_TIME0_RST = 0x000000FF,
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REG_PLL_TIME1_RST = 0x000000FF,
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REG_PLL_CPUX_BIAS_RST = 0x08100200,
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REG_PLL_AUDIO_BIAS_RST = 0x10100000,
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REG_PLL_VIDEO_BIAS_RST = 0x10100000,
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REG_PLL_VE_BIAS_RST = 0x10100000,
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REG_PLL_DDR_BIAS_RST = 0x81104000,
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REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
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REG_PLL_GPU_BIAS_RST = 0x10100000,
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REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
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REG_PLL_DE_BIAS_RST = 0x10100000,
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REG_PLL_CPUX_TUNING_RST = 0x0A101000,
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REG_PLL_DDR_TUNING_RST = 0x14880000,
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};
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static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwH3ClockCtlState *s = AW_H3_CCU(opaque);
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const uint32_t idx = REG_INDEX(offset);
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switch (offset) {
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case 0x308 ... AW_H3_CCU_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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return s->regs[idx];
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}
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static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwH3ClockCtlState *s = AW_H3_CCU(opaque);
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const uint32_t idx = REG_INDEX(offset);
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switch (offset) {
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case REG_DRAM_CFG: /* DRAM Configuration */
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val &= ~REG_DRAM_CFG_UPDATE;
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break;
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case REG_PLL_CPUX: /* PLL CPUX Control */
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case REG_PLL_AUDIO: /* PLL Audio Control */
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case REG_PLL_VIDEO: /* PLL Video Control */
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case REG_PLL_VE: /* PLL VE Control */
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case REG_PLL_DDR: /* PLL DDR Control */
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case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
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case REG_PLL_GPU: /* PLL GPU Control */
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case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
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case REG_PLL_DE: /* PLL Display Engine Control */
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if (val & REG_PLL_ENABLE) {
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val |= REG_PLL_LOCK;
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}
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break;
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case 0x308 ... AW_H3_CCU_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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}
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s->regs[idx] = (uint32_t) val;
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}
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static const MemoryRegionOps allwinner_h3_ccu_ops = {
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.read = allwinner_h3_ccu_read,
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.write = allwinner_h3_ccu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static void allwinner_h3_ccu_reset(DeviceState *dev)
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{
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AwH3ClockCtlState *s = AW_H3_CCU(dev);
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/* Set default values for registers */
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s->regs[REG_INDEX(REG_PLL_CPUX)] = REG_PLL_CPUX_RST;
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s->regs[REG_INDEX(REG_PLL_AUDIO)] = REG_PLL_AUDIO_RST;
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s->regs[REG_INDEX(REG_PLL_VIDEO)] = REG_PLL_VIDEO_RST;
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s->regs[REG_INDEX(REG_PLL_VE)] = REG_PLL_VE_RST;
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s->regs[REG_INDEX(REG_PLL_DDR)] = REG_PLL_DDR_RST;
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s->regs[REG_INDEX(REG_PLL_PERIPH0)] = REG_PLL_PERIPH0_RST;
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s->regs[REG_INDEX(REG_PLL_GPU)] = REG_PLL_GPU_RST;
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s->regs[REG_INDEX(REG_PLL_PERIPH1)] = REG_PLL_PERIPH1_RST;
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s->regs[REG_INDEX(REG_PLL_DE)] = REG_PLL_DE_RST;
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s->regs[REG_INDEX(REG_CPUX_AXI)] = REG_CPUX_AXI_RST;
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s->regs[REG_INDEX(REG_APB1)] = REG_APB1_RST;
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s->regs[REG_INDEX(REG_APB2)] = REG_APB2_RST;
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s->regs[REG_INDEX(REG_DRAM_CFG)] = REG_DRAM_CFG_RST;
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s->regs[REG_INDEX(REG_MBUS)] = REG_MBUS_RST;
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s->regs[REG_INDEX(REG_PLL_TIME0)] = REG_PLL_TIME0_RST;
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s->regs[REG_INDEX(REG_PLL_TIME1)] = REG_PLL_TIME1_RST;
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s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] = REG_PLL_CPUX_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] = REG_PLL_AUDIO_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] = REG_PLL_VIDEO_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_VE_BIAS)] = REG_PLL_VE_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] = REG_PLL_DDR_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] = REG_PLL_PERIPH0_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] = REG_PLL_GPU_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] = REG_PLL_PERIPH1_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_DE_BIAS)] = REG_PLL_DE_BIAS_RST;
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s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] = REG_PLL_CPUX_TUNING_RST;
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s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] = REG_PLL_DDR_TUNING_RST;
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}
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static void allwinner_h3_ccu_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwH3ClockCtlState *s = AW_H3_CCU(obj);
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/* Memory mapping */
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memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
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TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription allwinner_h3_ccu_vmstate = {
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.name = "allwinner-h3-ccu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = allwinner_h3_ccu_reset;
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dc->vmsd = &allwinner_h3_ccu_vmstate;
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}
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static const TypeInfo allwinner_h3_ccu_info = {
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.name = TYPE_AW_H3_CCU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_h3_ccu_init,
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.instance_size = sizeof(AwH3ClockCtlState),
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.class_init = allwinner_h3_ccu_class_init,
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};
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static void allwinner_h3_ccu_register(void)
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{
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type_register_static(&allwinner_h3_ccu_info);
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}
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type_init(allwinner_h3_ccu_register)
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