8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/*
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* ARMv7M CPU object
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*
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell <peter.maydell@linaro.org>
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*
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* This code is licensed under the GPL version 2 or later.
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*/
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#ifndef HW_ARM_ARMV7M_H
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#define HW_ARM_ARMV7M_H
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#include "hw/sysbus.h"
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#include "hw/intc/armv7m_nvic.h"
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#include "target/arm/idau.h"
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#include "qom/object.h"
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#define TYPE_BITBAND "ARM,bitband-memory"
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OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
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struct BitBandState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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AddressSpace source_as;
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MemoryRegion iomem;
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uint32_t base;
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MemoryRegion *source_memory;
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};
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#define TYPE_ARMV7M "armv7m"
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OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
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#define ARMV7M_NUM_BITBANDS 2
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/* ARMv7M container object.
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* + Unnamed GPIO input lines: external IRQ lines for the NVIC
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* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
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* If this GPIO is not wired up then the NVIC will default to performing
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* a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
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* + Property "cpu-type": CPU type to instantiate
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* + Property "num-irq": number of external IRQ lines
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* + Property "memory": MemoryRegion defining the physical address space
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* that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
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* devices will be automatically layered on top of this view.)
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* + Property "idau": IDAU interface (forwarded to CPU object)
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* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
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* + Property "vfp": enable VFP (forwarded to CPU object)
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* + Property "dsp": enable DSP (forwarded to CPU object)
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* + Property "enable-bitband": expose bitbanded IO
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*/
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struct ARMv7MState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NVICState nvic;
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BitBandState bitband[ARMV7M_NUM_BITBANDS];
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ARMCPU *cpu;
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/* MemoryRegion we pass to the CPU, with our devices layered on
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* top of the ones the board provides in board_memory.
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*/
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MemoryRegion container;
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/* Properties */
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char *cpu_type;
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/* MemoryRegion the board provides to us (with its devices, RAM, etc) */
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MemoryRegion *board_memory;
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Object *idau;
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uint32_t init_svtor;
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bool enable_bitband;
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bool start_powered_off;
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bool vfp;
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bool dsp;
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};
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#endif
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