957c52aed5
Test is wrong and the backend can never updated. It could have led to
a QEMU crash but since the firmware deactivates flash access if a valid
layout is not detected, it went unnoticed.
Reported-by: Coverity CID 1465223
Fixes: 35dde57662 ("ppc/pnv: Add a PNOR model")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211102162905.762078-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/*
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* QEMU PowerNV PNOR simple model
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*
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* Copyright (c) 2015-2019, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/blockdev.h"
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#include "hw/loader.h"
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#include "hw/ppc/pnv_pnor.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvPnor *s = PNV_PNOR(opaque);
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uint64_t ret = 0;
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int i;
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for (i = 0; i < size; i++) {
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ret |= (uint64_t) s->storage[addr + i] << (8 * (size - i - 1));
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}
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return ret;
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}
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static void pnv_pnor_update(PnvPnor *s, int offset, int size)
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{
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int offset_end;
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int ret;
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if (!s->blk || !blk_is_writable(s->blk)) {
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return;
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}
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offset_end = offset + size;
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offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
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offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
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ret = blk_pwrite(s->blk, offset, s->storage + offset,
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offset_end - offset, 0);
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if (ret < 0) {
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error_report("Could not update PNOR offset=0x%" PRIx32" : %s", offset,
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strerror(-ret));
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}
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}
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static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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PnvPnor *s = PNV_PNOR(opaque);
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int i;
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for (i = 0; i < size; i++) {
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s->storage[addr + i] = (data >> (8 * (size - i - 1))) & 0xFF;
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}
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pnv_pnor_update(s, addr, size);
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}
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/*
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* TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash
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* is BIG.
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*/
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static const MemoryRegionOps pnv_pnor_ops = {
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.read = pnv_pnor_read,
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.write = pnv_pnor_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void pnv_pnor_realize(DeviceState *dev, Error **errp)
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{
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PnvPnor *s = PNV_PNOR(dev);
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int ret;
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if (s->blk) {
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uint64_t perm = BLK_PERM_CONSISTENT_READ |
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(blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
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ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
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if (ret < 0) {
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return;
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}
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s->size = blk_getlength(s->blk);
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if (s->size <= 0) {
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error_setg(errp, "failed to get flash size");
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return;
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}
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s->storage = blk_blockalign(s->blk, s->size);
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if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
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error_setg(errp, "failed to read the initial flash content");
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return;
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}
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} else {
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s->storage = blk_blockalign(NULL, s->size);
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memset(s->storage, 0xFF, s->size);
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}
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memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
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TYPE_PNV_PNOR, s->size);
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}
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static Property pnv_pnor_properties[] = {
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DEFINE_PROP_INT64("size", PnvPnor, size, 128 * MiB),
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DEFINE_PROP_DRIVE("drive", PnvPnor, blk),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_pnor_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pnv_pnor_realize;
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device_class_set_props(dc, pnv_pnor_properties);
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}
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static const TypeInfo pnv_pnor_info = {
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.name = TYPE_PNV_PNOR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PnvPnor),
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.class_init = pnv_pnor_class_init,
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};
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static void pnv_pnor_register_types(void)
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{
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type_register_static(&pnv_pnor_info);
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}
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type_init(pnv_pnor_register_types)
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