2dfa91a2aa
This is a simple model of the POWER9 XIVE interrupt controller for the PowerNV machine which only addresses the needs of the skiboot firmware. The PowerNV model reuses the common XIVE framework developed for sPAPR as the fundamentals aspects are quite the same. The difference are outlined below. The controller initial BAR configuration is performed using the XSCOM bus from there, MMIO are used for further configuration. The MMIO regions exposed are : - Interrupt controller registers - ESB pages for IPIs and ENDs - Presenter MMIO (Not used) - Thread Interrupt Management Area MMIO, direct and indirect The virtualization controller MMIO region containing the IPI ESB pages and END ESB pages is sub-divided into "sets" which map portions of the VC region to the different ESB pages. These are modeled with custom address spaces and the XiveSource and XiveENDSource objects are sized to the maximum allowed by HW. The memory regions are resized at run-time using the configuration of EDT set translation table provided by the firmware. The XIVE virtualization structure tables (EAT, ENDT, NVTT) are now in the machine RAM and not in the hypervisor anymore. The firmware (skiboot) configures these tables using Virtual Structure Descriptor defining the characteristics of each table : SBE, EAS, END and NVT. These are later used to access the virtual interrupt entries. The internal cache of these tables in the interrupt controller is updated and invalidated using a set of registers. Still to address to complete the model but not fully required is the support for block grouping. Escalation support will be necessary for KVM guests. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
51 lines
2.1 KiB
Makefile
51 lines
2.1 KiB
Makefile
common-obj-$(CONFIG_HEATHROW_PIC) += heathrow_pic.o
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common-obj-$(CONFIG_I8259) += i8259_common.o i8259.o
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common-obj-$(CONFIG_PL190) += pl190.o
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common-obj-$(CONFIG_PUV3) += puv3_intc.o
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common-obj-$(CONFIG_XILINX) += xilinx_intc.o
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common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o
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common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
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common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o
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common-obj-$(CONFIG_LM32) += lm32_pic.o
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common-obj-$(CONFIG_REALVIEW) += realview_gic.o
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common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
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common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv2m.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
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common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
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common-obj-$(CONFIG_OPENPIC) += openpic.o
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common-obj-y += intc.o
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obj-$(CONFIG_APIC) += apic.o apic_common.o
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obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
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obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
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obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
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obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
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obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
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obj-$(CONFIG_GRLIB) += grlib_irqmp.o
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obj-$(CONFIG_IOAPIC) += ioapic.o
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obj-$(CONFIG_OMAP) += omap_intc.o
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obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
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obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
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obj-$(CONFIG_SH4) += sh_intc.o
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obj-$(CONFIG_XICS) += xics.o
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obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
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obj-$(CONFIG_XICS_KVM) += xics_kvm.o
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obj-$(CONFIG_XIVE) += xive.o
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obj-$(CONFIG_XIVE_SPAPR) += spapr_xive.o
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obj-$(CONFIG_POWERNV) += xics_pnv.o pnv_xive.o
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obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
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obj-$(CONFIG_S390_FLIC) += s390_flic.o
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obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o
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obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o
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obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
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obj-$(CONFIG_MIPS_CPS) += mips_gic.o
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obj-$(CONFIG_NIOS2) += nios2_iic.o
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obj-$(CONFIG_OMPIC) += ompic.o
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