1106 lines
30 KiB
C
1106 lines
30 KiB
C
/*
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* QEMU SM501 Device
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*
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* Copyright (c) 2008 Shin-ichiro KAWASAKI
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "hw.h"
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#include "pc.h"
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#include "console.h"
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#include "devices.h"
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/*
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* Status: 2008/11/02
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* - Minimum implementation for Linux console : mmio regs and CRT layer.
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* - Always updates full screen.
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*
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* TODO:
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* - Panel support
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* - Hardware cursor support
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* - Touch panel support
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* - USB support
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* - UART support
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* - Performance tuning
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*/
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//#define DEBUG_SM501
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//#define DEBUG_BITBLT
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#ifdef DEBUG_SM501
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#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
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#else
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#define SM501_DPRINTF(fmt, ...) do {} while(0)
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#endif
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#define MMIO_BASE_OFFSET 0x3e00000
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/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
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/* System Configuration area */
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/* System config base */
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#define SM501_SYS_CONFIG (0x000000)
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/* config 1 */
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#define SM501_SYSTEM_CONTROL (0x000000)
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#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
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#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
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#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
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#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
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#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
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#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
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#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
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/* miscellaneous control */
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#define SM501_MISC_CONTROL (0x000004)
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#define SM501_MISC_BUS_SH (0x0)
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#define SM501_MISC_BUS_PCI (0x1)
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#define SM501_MISC_BUS_XSCALE (0x2)
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#define SM501_MISC_BUS_NEC (0x6)
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#define SM501_MISC_BUS_MASK (0x7)
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#define SM501_MISC_VR_62MB (1<<3)
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#define SM501_MISC_CDR_RESET (1<<7)
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#define SM501_MISC_USB_LB (1<<8)
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#define SM501_MISC_USB_SLAVE (1<<9)
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#define SM501_MISC_BL_1 (1<<10)
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#define SM501_MISC_MC (1<<11)
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#define SM501_MISC_DAC_POWER (1<<12)
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#define SM501_MISC_IRQ_INVERT (1<<16)
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#define SM501_MISC_SH (1<<17)
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#define SM501_MISC_HOLD_EMPTY (0<<18)
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#define SM501_MISC_HOLD_8 (1<<18)
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#define SM501_MISC_HOLD_16 (2<<18)
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#define SM501_MISC_HOLD_24 (3<<18)
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#define SM501_MISC_HOLD_32 (4<<18)
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#define SM501_MISC_HOLD_MASK (7<<18)
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#define SM501_MISC_FREQ_12 (1<<24)
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#define SM501_MISC_PNL_24BIT (1<<25)
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#define SM501_MISC_8051_LE (1<<26)
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#define SM501_GPIO31_0_CONTROL (0x000008)
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#define SM501_GPIO63_32_CONTROL (0x00000C)
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#define SM501_DRAM_CONTROL (0x000010)
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/* command list */
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#define SM501_ARBTRTN_CONTROL (0x000014)
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/* command list */
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#define SM501_COMMAND_LIST_STATUS (0x000024)
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/* interrupt debug */
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#define SM501_RAW_IRQ_STATUS (0x000028)
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#define SM501_RAW_IRQ_CLEAR (0x000028)
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#define SM501_IRQ_STATUS (0x00002C)
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#define SM501_IRQ_MASK (0x000030)
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#define SM501_DEBUG_CONTROL (0x000034)
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/* power management */
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#define SM501_POWERMODE_P2X_SRC (1<<29)
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#define SM501_POWERMODE_V2X_SRC (1<<20)
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#define SM501_POWERMODE_M_SRC (1<<12)
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#define SM501_POWERMODE_M1_SRC (1<<4)
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#define SM501_CURRENT_GATE (0x000038)
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#define SM501_CURRENT_CLOCK (0x00003C)
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#define SM501_POWER_MODE_0_GATE (0x000040)
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#define SM501_POWER_MODE_0_CLOCK (0x000044)
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#define SM501_POWER_MODE_1_GATE (0x000048)
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#define SM501_POWER_MODE_1_CLOCK (0x00004C)
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#define SM501_SLEEP_MODE_GATE (0x000050)
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#define SM501_POWER_MODE_CONTROL (0x000054)
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/* power gates for units within the 501 */
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#define SM501_GATE_HOST (0)
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#define SM501_GATE_MEMORY (1)
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#define SM501_GATE_DISPLAY (2)
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#define SM501_GATE_2D_ENGINE (3)
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#define SM501_GATE_CSC (4)
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#define SM501_GATE_ZVPORT (5)
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#define SM501_GATE_GPIO (6)
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#define SM501_GATE_UART0 (7)
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#define SM501_GATE_UART1 (8)
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#define SM501_GATE_SSP (10)
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#define SM501_GATE_USB_HOST (11)
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#define SM501_GATE_USB_GADGET (12)
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#define SM501_GATE_UCONTROLLER (17)
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#define SM501_GATE_AC97 (18)
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/* panel clock */
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#define SM501_CLOCK_P2XCLK (24)
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/* crt clock */
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#define SM501_CLOCK_V2XCLK (16)
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/* main clock */
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#define SM501_CLOCK_MCLK (8)
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/* SDRAM controller clock */
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#define SM501_CLOCK_M1XCLK (0)
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/* config 2 */
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#define SM501_PCI_MASTER_BASE (0x000058)
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#define SM501_ENDIAN_CONTROL (0x00005C)
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#define SM501_DEVICEID (0x000060)
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/* 0x050100A0 */
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#define SM501_DEVICEID_SM501 (0x05010000)
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#define SM501_DEVICEID_IDMASK (0xffff0000)
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#define SM501_DEVICEID_REVMASK (0x000000ff)
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#define SM501_PLLCLOCK_COUNT (0x000064)
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#define SM501_MISC_TIMING (0x000068)
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#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
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#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
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/* GPIO base */
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#define SM501_GPIO (0x010000)
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#define SM501_GPIO_DATA_LOW (0x00)
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#define SM501_GPIO_DATA_HIGH (0x04)
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#define SM501_GPIO_DDR_LOW (0x08)
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#define SM501_GPIO_DDR_HIGH (0x0C)
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#define SM501_GPIO_IRQ_SETUP (0x10)
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#define SM501_GPIO_IRQ_STATUS (0x14)
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#define SM501_GPIO_IRQ_RESET (0x14)
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/* I2C controller base */
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#define SM501_I2C (0x010040)
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#define SM501_I2C_BYTE_COUNT (0x00)
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#define SM501_I2C_CONTROL (0x01)
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#define SM501_I2C_STATUS (0x02)
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#define SM501_I2C_RESET (0x02)
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#define SM501_I2C_SLAVE_ADDRESS (0x03)
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#define SM501_I2C_DATA (0x04)
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/* SSP base */
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#define SM501_SSP (0x020000)
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/* Uart 0 base */
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#define SM501_UART0 (0x030000)
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/* Uart 1 base */
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#define SM501_UART1 (0x030020)
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/* USB host port base */
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#define SM501_USB_HOST (0x040000)
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/* USB slave/gadget base */
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#define SM501_USB_GADGET (0x060000)
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/* USB slave/gadget data port base */
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#define SM501_USB_GADGET_DATA (0x070000)
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/* Display controller/video engine base */
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#define SM501_DC (0x080000)
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/* common defines for the SM501 address registers */
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#define SM501_ADDR_FLIP (1<<31)
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#define SM501_ADDR_EXT (1<<27)
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#define SM501_ADDR_CS1 (1<<26)
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#define SM501_ADDR_MASK (0x3f << 26)
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#define SM501_FIFO_MASK (0x3 << 16)
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#define SM501_FIFO_1 (0x0 << 16)
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#define SM501_FIFO_3 (0x1 << 16)
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#define SM501_FIFO_7 (0x2 << 16)
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#define SM501_FIFO_11 (0x3 << 16)
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/* common registers for panel and the crt */
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#define SM501_OFF_DC_H_TOT (0x000)
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#define SM501_OFF_DC_V_TOT (0x008)
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#define SM501_OFF_DC_H_SYNC (0x004)
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#define SM501_OFF_DC_V_SYNC (0x00C)
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#define SM501_DC_PANEL_CONTROL (0x000)
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#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
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#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
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#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
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#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
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#define SM501_DC_PANEL_CONTROL_DP (1<<23)
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#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
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#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
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#define SM501_DC_PANEL_CONTROL_DE (1<<20)
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#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
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#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
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#define SM501_DC_PANEL_CONTROL_CP (1<<14)
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#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
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#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
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#define SM501_DC_PANEL_CONTROL_CK (1<<9)
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#define SM501_DC_PANEL_CONTROL_TE (1<<8)
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#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
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#define SM501_DC_PANEL_CONTROL_VP (1<<6)
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#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
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#define SM501_DC_PANEL_CONTROL_HP (1<<4)
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#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
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#define SM501_DC_PANEL_CONTROL_EN (1<<2)
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#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
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#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
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#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
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#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
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#define SM501_DC_PANEL_COLOR_KEY (0x008)
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#define SM501_DC_PANEL_FB_ADDR (0x00C)
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#define SM501_DC_PANEL_FB_OFFSET (0x010)
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#define SM501_DC_PANEL_FB_WIDTH (0x014)
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#define SM501_DC_PANEL_FB_HEIGHT (0x018)
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#define SM501_DC_PANEL_TL_LOC (0x01C)
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#define SM501_DC_PANEL_BR_LOC (0x020)
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#define SM501_DC_PANEL_H_TOT (0x024)
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#define SM501_DC_PANEL_H_SYNC (0x028)
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#define SM501_DC_PANEL_V_TOT (0x02C)
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#define SM501_DC_PANEL_V_SYNC (0x030)
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#define SM501_DC_PANEL_CUR_LINE (0x034)
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#define SM501_DC_VIDEO_CONTROL (0x040)
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#define SM501_DC_VIDEO_FB0_ADDR (0x044)
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#define SM501_DC_VIDEO_FB_WIDTH (0x048)
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#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
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#define SM501_DC_VIDEO_TL_LOC (0x050)
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#define SM501_DC_VIDEO_BR_LOC (0x054)
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#define SM501_DC_VIDEO_SCALE (0x058)
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#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
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#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
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#define SM501_DC_VIDEO_FB1_ADDR (0x064)
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#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
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#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
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#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
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#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
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#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
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#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
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#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
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#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
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#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
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#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
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#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
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#define SM501_DC_PANEL_HWC_BASE (0x0F0)
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#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
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#define SM501_DC_PANEL_HWC_LOC (0x0F4)
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#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
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#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
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#define SM501_HWC_EN (1<<31)
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#define SM501_OFF_HWC_ADDR (0x00)
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#define SM501_OFF_HWC_LOC (0x04)
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#define SM501_OFF_HWC_COLOR_1_2 (0x08)
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#define SM501_OFF_HWC_COLOR_3 (0x0C)
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#define SM501_DC_ALPHA_CONTROL (0x100)
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#define SM501_DC_ALPHA_FB_ADDR (0x104)
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#define SM501_DC_ALPHA_FB_OFFSET (0x108)
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#define SM501_DC_ALPHA_TL_LOC (0x10C)
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#define SM501_DC_ALPHA_BR_LOC (0x110)
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#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
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#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
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#define SM501_DC_CRT_CONTROL (0x200)
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#define SM501_DC_CRT_CONTROL_TVP (1<<15)
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#define SM501_DC_CRT_CONTROL_CP (1<<14)
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#define SM501_DC_CRT_CONTROL_VSP (1<<13)
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#define SM501_DC_CRT_CONTROL_HSP (1<<12)
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#define SM501_DC_CRT_CONTROL_VS (1<<11)
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#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
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#define SM501_DC_CRT_CONTROL_SEL (1<<9)
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#define SM501_DC_CRT_CONTROL_TE (1<<8)
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#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
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#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
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#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
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#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
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#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
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#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
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#define SM501_DC_CRT_FB_ADDR (0x204)
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#define SM501_DC_CRT_FB_OFFSET (0x208)
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#define SM501_DC_CRT_H_TOT (0x20C)
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#define SM501_DC_CRT_H_SYNC (0x210)
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#define SM501_DC_CRT_V_TOT (0x214)
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#define SM501_DC_CRT_V_SYNC (0x218)
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#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
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#define SM501_DC_CRT_CUR_LINE (0x220)
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#define SM501_DC_CRT_MONITOR_DETECT (0x224)
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#define SM501_DC_CRT_HWC_BASE (0x230)
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#define SM501_DC_CRT_HWC_ADDR (0x230)
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#define SM501_DC_CRT_HWC_LOC (0x234)
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#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
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#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
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#define SM501_DC_PANEL_PALETTE (0x400)
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#define SM501_DC_VIDEO_PALETTE (0x800)
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#define SM501_DC_CRT_PALETTE (0xC00)
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/* Zoom Video port base */
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#define SM501_ZVPORT (0x090000)
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/* AC97/I2S base */
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#define SM501_AC97 (0x0A0000)
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/* 8051 micro controller base */
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#define SM501_UCONTROLLER (0x0B0000)
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/* 8051 micro controller SRAM base */
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#define SM501_UCONTROLLER_SRAM (0x0C0000)
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/* DMA base */
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#define SM501_DMA (0x0D0000)
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/* 2d engine base */
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#define SM501_2D_ENGINE (0x100000)
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#define SM501_2D_SOURCE (0x00)
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#define SM501_2D_DESTINATION (0x04)
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#define SM501_2D_DIMENSION (0x08)
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#define SM501_2D_CONTROL (0x0C)
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#define SM501_2D_PITCH (0x10)
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#define SM501_2D_FOREGROUND (0x14)
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#define SM501_2D_BACKGROUND (0x18)
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#define SM501_2D_STRETCH (0x1C)
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#define SM501_2D_COLOR_COMPARE (0x20)
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#define SM501_2D_COLOR_COMPARE_MASK (0x24)
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#define SM501_2D_MASK (0x28)
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|
#define SM501_2D_CLIP_TL (0x2C)
|
|
#define SM501_2D_CLIP_BR (0x30)
|
|
#define SM501_2D_MONO_PATTERN_LOW (0x34)
|
|
#define SM501_2D_MONO_PATTERN_HIGH (0x38)
|
|
#define SM501_2D_WINDOW_WIDTH (0x3C)
|
|
#define SM501_2D_SOURCE_BASE (0x40)
|
|
#define SM501_2D_DESTINATION_BASE (0x44)
|
|
#define SM501_2D_ALPHA (0x48)
|
|
#define SM501_2D_WRAP (0x4C)
|
|
#define SM501_2D_STATUS (0x50)
|
|
|
|
#define SM501_CSC_Y_SOURCE_BASE (0xC8)
|
|
#define SM501_CSC_CONSTANTS (0xCC)
|
|
#define SM501_CSC_Y_SOURCE_X (0xD0)
|
|
#define SM501_CSC_Y_SOURCE_Y (0xD4)
|
|
#define SM501_CSC_U_SOURCE_BASE (0xD8)
|
|
#define SM501_CSC_V_SOURCE_BASE (0xDC)
|
|
#define SM501_CSC_SOURCE_DIMENSION (0xE0)
|
|
#define SM501_CSC_SOURCE_PITCH (0xE4)
|
|
#define SM501_CSC_DESTINATION (0xE8)
|
|
#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
|
|
#define SM501_CSC_DESTINATION_PITCH (0xF0)
|
|
#define SM501_CSC_SCALE_FACTOR (0xF4)
|
|
#define SM501_CSC_DESTINATION_BASE (0xF8)
|
|
#define SM501_CSC_CONTROL (0xFC)
|
|
|
|
/* 2d engine data port base */
|
|
#define SM501_2D_ENGINE_DATA (0x110000)
|
|
|
|
/* end of register definitions */
|
|
|
|
|
|
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
|
|
static const uint32_t sm501_mem_local_size[] = {
|
|
[0] = 4*1024*1024,
|
|
[1] = 8*1024*1024,
|
|
[2] = 16*1024*1024,
|
|
[3] = 32*1024*1024,
|
|
[4] = 64*1024*1024,
|
|
[5] = 2*1024*1024,
|
|
};
|
|
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
|
|
|
|
typedef struct SM501State {
|
|
/* graphic console status */
|
|
DisplayState *ds;
|
|
|
|
/* status & internal resources */
|
|
target_phys_addr_t base;
|
|
uint32_t local_mem_size_index;
|
|
uint8_t * local_mem;
|
|
ram_addr_t local_mem_offset;
|
|
uint32_t last_width;
|
|
uint32_t last_height;
|
|
|
|
/* mmio registers */
|
|
uint32_t system_control;
|
|
uint32_t misc_control;
|
|
uint32_t gpio_31_0_control;
|
|
uint32_t gpio_63_32_control;
|
|
uint32_t dram_control;
|
|
uint32_t irq_mask;
|
|
uint32_t misc_timing;
|
|
uint32_t power_mode_control;
|
|
|
|
uint32_t uart0_ier;
|
|
uint32_t uart0_lcr;
|
|
uint32_t uart0_mcr;
|
|
uint32_t uart0_scr;
|
|
|
|
uint8_t dc_palette[0x400 * 3];
|
|
|
|
uint32_t dc_panel_control;
|
|
uint32_t dc_panel_panning_control;
|
|
uint32_t dc_panel_fb_addr;
|
|
uint32_t dc_panel_fb_offset;
|
|
uint32_t dc_panel_fb_width;
|
|
uint32_t dc_panel_fb_height;
|
|
uint32_t dc_panel_tl_location;
|
|
uint32_t dc_panel_br_location;
|
|
uint32_t dc_panel_h_total;
|
|
uint32_t dc_panel_h_sync;
|
|
uint32_t dc_panel_v_total;
|
|
uint32_t dc_panel_v_sync;
|
|
|
|
uint32_t dc_panel_hwc_addr;
|
|
uint32_t dc_panel_hwc_location;
|
|
uint32_t dc_panel_hwc_color_1_2;
|
|
uint32_t dc_panel_hwc_color_3;
|
|
|
|
uint32_t dc_crt_control;
|
|
uint32_t dc_crt_fb_addr;
|
|
uint32_t dc_crt_fb_offset;
|
|
uint32_t dc_crt_h_total;
|
|
uint32_t dc_crt_h_sync;
|
|
uint32_t dc_crt_v_total;
|
|
uint32_t dc_crt_v_sync;
|
|
|
|
uint32_t dc_crt_hwc_addr;
|
|
uint32_t dc_crt_hwc_location;
|
|
uint32_t dc_crt_hwc_color_1_2;
|
|
uint32_t dc_crt_hwc_color_3;
|
|
|
|
} SM501State;
|
|
|
|
static uint32_t get_local_mem_size_index(uint32_t size)
|
|
{
|
|
uint32_t norm_size = 0;
|
|
int i, index = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
|
|
uint32_t new_size = sm501_mem_local_size[i];
|
|
if (new_size >= size) {
|
|
if (norm_size == 0 || norm_size > new_size) {
|
|
norm_size = new_size;
|
|
index = i;
|
|
}
|
|
}
|
|
}
|
|
|
|
return index;
|
|
}
|
|
|
|
static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
uint32_t ret = 0;
|
|
SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
|
|
|
|
switch(addr) {
|
|
case SM501_SYSTEM_CONTROL:
|
|
ret = s->system_control;
|
|
break;
|
|
case SM501_MISC_CONTROL:
|
|
ret = s->misc_control;
|
|
break;
|
|
case SM501_GPIO31_0_CONTROL:
|
|
ret = s->gpio_31_0_control;
|
|
break;
|
|
case SM501_GPIO63_32_CONTROL:
|
|
ret = s->gpio_63_32_control;
|
|
break;
|
|
case SM501_DEVICEID:
|
|
ret = 0x050100A0;
|
|
break;
|
|
case SM501_DRAM_CONTROL:
|
|
ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
|
|
break;
|
|
case SM501_IRQ_MASK:
|
|
ret = s->irq_mask;
|
|
break;
|
|
case SM501_MISC_TIMING:
|
|
/* TODO : simulate gate control */
|
|
ret = s->misc_timing;
|
|
break;
|
|
case SM501_CURRENT_GATE:
|
|
/* TODO : simulate gate control */
|
|
ret = 0x00021807;
|
|
break;
|
|
case SM501_CURRENT_CLOCK:
|
|
ret = 0x2A1A0A09;
|
|
break;
|
|
case SM501_POWER_MODE_CONTROL:
|
|
ret = s->power_mode_control;
|
|
break;
|
|
|
|
default:
|
|
printf("sm501 system config : not implemented register read."
|
|
" addr=%x\n", (int)addr);
|
|
assert(0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sm501_system_config_write(void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
|
|
addr, value);
|
|
|
|
switch(addr) {
|
|
case SM501_SYSTEM_CONTROL:
|
|
s->system_control = value & 0xE300B8F7;
|
|
break;
|
|
case SM501_MISC_CONTROL:
|
|
s->misc_control = value & 0xFF7FFF20;
|
|
break;
|
|
case SM501_GPIO31_0_CONTROL:
|
|
s->gpio_31_0_control = value;
|
|
break;
|
|
case SM501_GPIO63_32_CONTROL:
|
|
s->gpio_63_32_control = value;
|
|
break;
|
|
case SM501_DRAM_CONTROL:
|
|
s->local_mem_size_index = (value >> 13) & 0x7;
|
|
/* rODO : check validity of size change */
|
|
s->dram_control |= value & 0x7FFFFFC3;
|
|
break;
|
|
case SM501_IRQ_MASK:
|
|
s->irq_mask = value;
|
|
break;
|
|
case SM501_MISC_TIMING:
|
|
s->misc_timing = value & 0xF31F1FFF;
|
|
break;
|
|
case SM501_POWER_MODE_0_GATE:
|
|
case SM501_POWER_MODE_1_GATE:
|
|
case SM501_POWER_MODE_0_CLOCK:
|
|
case SM501_POWER_MODE_1_CLOCK:
|
|
/* TODO : simulate gate & clock control */
|
|
break;
|
|
case SM501_POWER_MODE_CONTROL:
|
|
s->power_mode_control = value & 0x00000003;
|
|
break;
|
|
|
|
default:
|
|
printf("sm501 system config : not implemented register write."
|
|
" addr=%x, val=%x\n", (int)addr, value);
|
|
assert(0);
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const sm501_system_config_readfn[] = {
|
|
NULL,
|
|
NULL,
|
|
&sm501_system_config_read,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const sm501_system_config_writefn[] = {
|
|
NULL,
|
|
NULL,
|
|
&sm501_system_config_write,
|
|
};
|
|
|
|
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
|
|
|
|
/* TODO : consider BYTE/WORD access */
|
|
/* TODO : consider endian */
|
|
|
|
assert(0 <= addr && addr < 0x400 * 3);
|
|
return *(uint32_t*)&s->dc_palette[addr];
|
|
}
|
|
|
|
static void sm501_palette_write(void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
|
|
(int)addr, value);
|
|
|
|
/* TODO : consider BYTE/WORD access */
|
|
/* TODO : consider endian */
|
|
|
|
assert(0 <= addr && addr < 0x400 * 3);
|
|
*(uint32_t*)&s->dc_palette[addr] = value;
|
|
}
|
|
|
|
static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
uint32_t ret = 0;
|
|
SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
|
|
|
|
switch(addr) {
|
|
|
|
case SM501_DC_PANEL_CONTROL:
|
|
ret = s->dc_panel_control;
|
|
break;
|
|
case SM501_DC_PANEL_PANNING_CONTROL:
|
|
ret = s->dc_panel_panning_control;
|
|
break;
|
|
case SM501_DC_PANEL_FB_ADDR:
|
|
ret = s->dc_panel_fb_addr;
|
|
break;
|
|
case SM501_DC_PANEL_FB_OFFSET:
|
|
ret = s->dc_panel_fb_offset;
|
|
break;
|
|
case SM501_DC_PANEL_FB_WIDTH:
|
|
ret = s->dc_panel_fb_width;
|
|
break;
|
|
case SM501_DC_PANEL_FB_HEIGHT:
|
|
ret = s->dc_panel_fb_height;
|
|
break;
|
|
case SM501_DC_PANEL_TL_LOC:
|
|
ret = s->dc_panel_tl_location;
|
|
break;
|
|
case SM501_DC_PANEL_BR_LOC:
|
|
ret = s->dc_panel_br_location;
|
|
break;
|
|
|
|
case SM501_DC_PANEL_H_TOT:
|
|
ret = s->dc_panel_h_total;
|
|
break;
|
|
case SM501_DC_PANEL_H_SYNC:
|
|
ret = s->dc_panel_h_sync;
|
|
break;
|
|
case SM501_DC_PANEL_V_TOT:
|
|
ret = s->dc_panel_v_total;
|
|
break;
|
|
case SM501_DC_PANEL_V_SYNC:
|
|
ret = s->dc_panel_v_sync;
|
|
break;
|
|
|
|
case SM501_DC_CRT_CONTROL:
|
|
ret = s->dc_crt_control;
|
|
break;
|
|
case SM501_DC_CRT_FB_ADDR:
|
|
ret = s->dc_crt_fb_addr;
|
|
break;
|
|
case SM501_DC_CRT_FB_OFFSET:
|
|
ret = s->dc_crt_fb_offset;
|
|
break;
|
|
case SM501_DC_CRT_H_TOT:
|
|
ret = s->dc_crt_h_total;
|
|
break;
|
|
case SM501_DC_CRT_H_SYNC:
|
|
ret = s->dc_crt_h_sync;
|
|
break;
|
|
case SM501_DC_CRT_V_TOT:
|
|
ret = s->dc_crt_v_total;
|
|
break;
|
|
case SM501_DC_CRT_V_SYNC:
|
|
ret = s->dc_crt_v_sync;
|
|
break;
|
|
|
|
case SM501_DC_CRT_HWC_ADDR:
|
|
ret = s->dc_crt_hwc_addr;
|
|
break;
|
|
case SM501_DC_CRT_HWC_LOC:
|
|
ret = s->dc_crt_hwc_addr;
|
|
break;
|
|
case SM501_DC_CRT_HWC_COLOR_1_2:
|
|
ret = s->dc_crt_hwc_addr;
|
|
break;
|
|
case SM501_DC_CRT_HWC_COLOR_3:
|
|
ret = s->dc_crt_hwc_addr;
|
|
break;
|
|
|
|
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
|
|
ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
|
|
break;
|
|
|
|
default:
|
|
printf("sm501 disp ctrl : not implemented register read."
|
|
" addr=%x\n", (int)addr);
|
|
assert(0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void sm501_disp_ctrl_write(void *opaque,
|
|
target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
SM501State * s = (SM501State *)opaque;
|
|
SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
|
|
addr, value);
|
|
|
|
switch(addr) {
|
|
case SM501_DC_PANEL_CONTROL:
|
|
s->dc_panel_control = value & 0x0FFF73FF;
|
|
break;
|
|
case SM501_DC_PANEL_PANNING_CONTROL:
|
|
s->dc_panel_panning_control = value & 0xFF3FFF3F;
|
|
break;
|
|
case SM501_DC_PANEL_FB_ADDR:
|
|
s->dc_panel_fb_addr = value & 0x8FFFFFF0;
|
|
break;
|
|
case SM501_DC_PANEL_FB_OFFSET:
|
|
s->dc_panel_fb_offset = value & 0x3FF03FF0;
|
|
break;
|
|
case SM501_DC_PANEL_FB_WIDTH:
|
|
s->dc_panel_fb_width = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_FB_HEIGHT:
|
|
s->dc_panel_fb_height = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_TL_LOC:
|
|
s->dc_panel_tl_location = value & 0x07FF07FF;
|
|
break;
|
|
case SM501_DC_PANEL_BR_LOC:
|
|
s->dc_panel_br_location = value & 0x07FF07FF;
|
|
break;
|
|
|
|
case SM501_DC_PANEL_H_TOT:
|
|
s->dc_panel_h_total = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_H_SYNC:
|
|
s->dc_panel_h_sync = value & 0x00FF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_V_TOT:
|
|
s->dc_panel_v_total = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_V_SYNC:
|
|
s->dc_panel_v_sync = value & 0x003F0FFF;
|
|
break;
|
|
|
|
case SM501_DC_PANEL_HWC_ADDR:
|
|
s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
|
|
break;
|
|
case SM501_DC_PANEL_HWC_LOC:
|
|
s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_PANEL_HWC_COLOR_1_2:
|
|
s->dc_panel_hwc_addr = value;
|
|
break;
|
|
case SM501_DC_PANEL_HWC_COLOR_3:
|
|
s->dc_panel_hwc_addr = value & 0x0000FFFF;
|
|
break;
|
|
|
|
case SM501_DC_CRT_CONTROL:
|
|
s->dc_crt_control = value & 0x0003FFFF;
|
|
break;
|
|
case SM501_DC_CRT_FB_ADDR:
|
|
s->dc_crt_fb_addr = value & 0x8FFFFFF0;
|
|
break;
|
|
case SM501_DC_CRT_FB_OFFSET:
|
|
s->dc_crt_fb_offset = value & 0x3FF03FF0;
|
|
break;
|
|
case SM501_DC_CRT_H_TOT:
|
|
s->dc_crt_h_total = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_CRT_H_SYNC:
|
|
s->dc_crt_h_sync = value & 0x00FF0FFF;
|
|
break;
|
|
case SM501_DC_CRT_V_TOT:
|
|
s->dc_crt_v_total = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_CRT_V_SYNC:
|
|
s->dc_crt_v_sync = value & 0x003F0FFF;
|
|
break;
|
|
|
|
case SM501_DC_CRT_HWC_ADDR:
|
|
s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
|
|
break;
|
|
case SM501_DC_CRT_HWC_LOC:
|
|
s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
|
|
break;
|
|
case SM501_DC_CRT_HWC_COLOR_1_2:
|
|
s->dc_crt_hwc_addr = value;
|
|
break;
|
|
case SM501_DC_CRT_HWC_COLOR_3:
|
|
s->dc_crt_hwc_addr = value & 0x0000FFFF;
|
|
break;
|
|
|
|
case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
|
|
sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
|
|
break;
|
|
|
|
default:
|
|
printf("sm501 disp ctrl : not implemented register write."
|
|
" addr=%x, val=%x\n", (int)addr, value);
|
|
assert(0);
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const sm501_disp_ctrl_readfn[] = {
|
|
NULL,
|
|
NULL,
|
|
&sm501_disp_ctrl_read,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const sm501_disp_ctrl_writefn[] = {
|
|
NULL,
|
|
NULL,
|
|
&sm501_disp_ctrl_write,
|
|
};
|
|
|
|
/* draw line functions for all console modes */
|
|
|
|
#include "pixel_ops.h"
|
|
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typedef void draw_line_func(uint8_t *d, const uint8_t *s,
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int width, const uint32_t *pal);
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#define DEPTH 8
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#include "sm501_template.h"
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#define DEPTH 15
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#include "sm501_template.h"
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#define BGR_FORMAT
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#define DEPTH 15
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#include "sm501_template.h"
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#define DEPTH 16
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#include "sm501_template.h"
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#define BGR_FORMAT
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#define DEPTH 16
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#include "sm501_template.h"
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#define DEPTH 32
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#include "sm501_template.h"
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#define BGR_FORMAT
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#define DEPTH 32
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#include "sm501_template.h"
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static draw_line_func * draw_line8_funcs[] = {
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draw_line8_8,
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draw_line8_15,
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draw_line8_16,
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draw_line8_32,
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draw_line8_32bgr,
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draw_line8_15bgr,
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draw_line8_16bgr,
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};
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static draw_line_func * draw_line16_funcs[] = {
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draw_line16_8,
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draw_line16_15,
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draw_line16_16,
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draw_line16_32,
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draw_line16_32bgr,
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draw_line16_15bgr,
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draw_line16_16bgr,
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};
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static draw_line_func * draw_line32_funcs[] = {
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draw_line32_8,
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draw_line32_15,
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draw_line32_16,
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draw_line32_32,
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draw_line32_32bgr,
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draw_line32_15bgr,
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draw_line32_16bgr,
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};
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static inline int get_depth_index(DisplayState *s)
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{
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switch(ds_get_bits_per_pixel(s)) {
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default:
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case 8:
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return 0;
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case 15:
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return 1;
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case 16:
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return 2;
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case 32:
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if (is_surface_bgr(s->surface))
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return 4;
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else
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return 3;
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}
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}
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static void sm501_draw_crt(SM501State * s)
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{
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int y;
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int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
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int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
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uint8_t * src = s->local_mem;
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int src_bpp = 0;
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int dst_bpp = ds_get_bytes_per_pixel(s->ds) + (ds_get_bits_per_pixel(s->ds) % 8 ? 1 : 0);
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uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
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- SM501_DC_PANEL_PALETTE];
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int ds_depth_index = get_depth_index(s->ds);
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draw_line_func * draw_line = NULL;
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int full_update = 0;
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int y_start = -1;
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int page_min = 0x7fffffff;
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int page_max = -1;
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ram_addr_t offset = s->local_mem_offset;
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/* choose draw_line function */
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switch (s->dc_crt_control & 3) {
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case SM501_DC_CRT_CONTROL_8BPP:
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src_bpp = 1;
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draw_line = draw_line8_funcs[ds_depth_index];
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break;
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case SM501_DC_CRT_CONTROL_16BPP:
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src_bpp = 2;
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draw_line = draw_line16_funcs[ds_depth_index];
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break;
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case SM501_DC_CRT_CONTROL_32BPP:
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src_bpp = 4;
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draw_line = draw_line32_funcs[ds_depth_index];
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break;
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default:
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printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
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s->dc_crt_control);
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assert(0);
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break;
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}
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/* adjust console size */
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if (s->last_width != width || s->last_height != height) {
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qemu_console_resize(s->ds, width, height);
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s->last_width = width;
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s->last_height = height;
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full_update = 1;
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}
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/* draw each line according to conditions */
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for (y = 0; y < height; y++) {
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int update = full_update;
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ram_addr_t page0 = offset & TARGET_PAGE_MASK;
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ram_addr_t page1 = (offset + width * src_bpp - 1) & TARGET_PAGE_MASK;
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ram_addr_t page;
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/* check dirty flags for each line */
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for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
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if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
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update = 1;
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/* draw line and change status */
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if (update) {
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draw_line(&(ds_get_data(s->ds)[y * width * dst_bpp]), src, width, palette);
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if (y_start < 0)
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y_start = y;
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if (page0 < page_min)
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page_min = page0;
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if (page1 > page_max)
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page_max = page1;
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} else {
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if (y_start >= 0) {
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/* flush to display */
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dpy_update(s->ds, 0, y_start, width, y - y_start);
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y_start = -1;
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}
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}
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src += width * src_bpp;
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offset += width * src_bpp;
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}
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/* complete flush to display */
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if (y_start >= 0)
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dpy_update(s->ds, 0, y_start, width, y - y_start);
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/* clear dirty flags */
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if (page_max != -1)
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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}
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static void sm501_update_display(void *opaque)
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{
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SM501State * s = (SM501State *)opaque;
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if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
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sm501_draw_crt(s);
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}
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void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
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CharDriverState *chr)
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{
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SM501State * s;
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int sm501_system_config_index;
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int sm501_disp_ctrl_index;
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/* allocate management data region */
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s = (SM501State *)qemu_mallocz(sizeof(SM501State));
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s->base = base;
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s->local_mem_size_index
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= get_local_mem_size_index(local_mem_bytes);
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SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
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s->local_mem_size_index);
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s->system_control = 0x00100000;
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s->misc_control = 0x00001000; /* assumes SH, active=low */
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s->dc_panel_control = 0x00010000;
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s->dc_crt_control = 0x00010000;
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/* allocate local memory */
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s->local_mem_offset = qemu_ram_alloc(local_mem_bytes);
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s->local_mem = qemu_get_ram_ptr(s->local_mem_offset);
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cpu_register_physical_memory(base, local_mem_bytes, s->local_mem_offset);
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/* map mmio */
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sm501_system_config_index
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= cpu_register_io_memory(sm501_system_config_readfn,
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sm501_system_config_writefn, s);
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cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
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0x6c, sm501_system_config_index);
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sm501_disp_ctrl_index = cpu_register_io_memory(sm501_disp_ctrl_readfn,
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sm501_disp_ctrl_writefn, s);
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cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
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0x1000, sm501_disp_ctrl_index);
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/* bridge to usb host emulation module */
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usb_ohci_init_sm501(base + MMIO_BASE_OFFSET + SM501_USB_HOST, base,
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2, -1, irq);
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/* bridge to serial emulation module */
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if (chr)
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serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
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NULL, /* TODO : chain irq to IRL */
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115200, chr, 1);
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/* create qemu graphic console */
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s->ds = graphic_console_init(sm501_update_display, NULL,
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NULL, NULL, s);
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}
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