f57a516039
flush_icache_range takes two address parameters which must be large enough to address any address of the host. For hosts with sizeof(unsigned long) == sizeof(void *), this patch changes nothing. All currently supported hosts fall into this category. For w64 hosts, sizeof(unsigned long) is 4 while sizeof(void *) is 8, so the use of tcg_target_ulong is needed for i386 and tci (the tcg targets which work with w64). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
130 lines
4.2 KiB
C
130 lines
4.2 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_I386 1
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//#define TCG_TARGET_WORDS_BIGENDIAN
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#if TCG_TARGET_REG_BITS == 64
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# define TCG_TARGET_NB_REGS 16
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#else
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# define TCG_TARGET_NB_REGS 8
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#endif
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typedef enum {
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TCG_REG_EAX = 0,
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TCG_REG_ECX,
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TCG_REG_EDX,
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TCG_REG_EBX,
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TCG_REG_ESP,
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TCG_REG_EBP,
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TCG_REG_ESI,
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TCG_REG_EDI,
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/* 64-bit registers; always define the symbols to avoid
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too much if-deffing. */
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_RAX = TCG_REG_EAX,
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TCG_REG_RCX = TCG_REG_ECX,
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TCG_REG_RDX = TCG_REG_EDX,
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TCG_REG_RBX = TCG_REG_EBX,
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TCG_REG_RSP = TCG_REG_ESP,
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TCG_REG_RBP = TCG_REG_EBP,
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TCG_REG_RSI = TCG_REG_ESI,
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TCG_REG_RDI = TCG_REG_EDI,
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} TCGReg;
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#define TCG_CT_CONST_S32 0x100
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#define TCG_CT_CONST_U32 0x200
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_ESP
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_div2_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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#endif
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
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((ofs) == 0 && (len) == 16))
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#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
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#define TCG_TARGET_HAS_GUEST_BASE
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/* Note: must be synced with dyngen-exec.h */
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#if TCG_TARGET_REG_BITS == 64
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# define TCG_AREG0 TCG_REG_R14
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#else
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# define TCG_AREG0 TCG_REG_EBP
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#endif
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static inline void flush_icache_range(tcg_target_ulong start,
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tcg_target_ulong stop)
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{
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}
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