66564c31e4
When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.
This looks to be caused by 2 issues in the openrisc interrupt handling
logic.
1. After clearing an interrupt the openrisc_cpu_set_irq handler will
always clear PICSR. This is not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
296 lines
8.4 KiB
C
296 lines
8.4 KiB
C
/*
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* QEMU OpenRISC CPU
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*
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* Copyright (c) 2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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cpu->env.pc = value;
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cpu->env.dflag = 0;
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}
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static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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cpu->env.pc = tb->pc;
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}
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static bool openrisc_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_TIMER);
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}
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static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->print_insn = print_insn_or1k;
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}
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static void openrisc_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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OpenRISCCPU *cpu = OPENRISC_CPU(s);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
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occ->parent_reset(dev);
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memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
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cpu->env.pc = 0x100;
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cpu->env.sr = SR_FO | SR_SM;
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cpu->env.lock_addr = -1;
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s->exception_index = -1;
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cpu_set_fpcsr(&cpu->env, 0);
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#ifndef CONFIG_USER_ONLY
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cpu->env.picmr = 0x00000000;
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cpu->env.picsr = 0x00000000;
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cpu->env.ttmr = 0x00000000;
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
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{
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OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
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CPUState *cs = CPU(cpu);
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uint32_t irq_bit;
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if (irq > 31 || irq < 0) {
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return;
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}
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irq_bit = 1U << irq;
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if (level) {
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cpu->env.picsr |= irq_bit;
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} else {
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cpu->env.picsr &= ~irq_bit;
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}
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if (cpu->env.picsr & cpu->env.picmr) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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#endif
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static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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occ->parent_realize(dev, errp);
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}
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static void openrisc_cpu_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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#ifndef CONFIG_USER_ONLY
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qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
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#endif
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}
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/* CPU models */
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static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
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object_class_is_abstract(oc))) {
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return NULL;
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}
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return oc;
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}
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static void or1200_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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cpu->env.vr = 0x13000008;
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
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cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
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CPUCFGR_EVBARP;
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/* 1Way, TLB_SIZE entries. */
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
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| (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
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| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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}
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static void openrisc_any_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */
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cpu->env.vr2 = 0; /* No version specific id */
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cpu->env.avr = 0x01030000; /* Architecture v1.3 */
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
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cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
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CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
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/* 1Way, TLB_SIZE entries. */
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
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| (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
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| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
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}
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#ifndef CONFIG_USER_ONLY
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps openrisc_sysemu_ops = {
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.get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
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};
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#endif
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps openrisc_tcg_ops = {
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.initialize = openrisc_translate_init,
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.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = openrisc_cpu_tlb_fill,
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.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
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.do_interrupt = openrisc_cpu_do_interrupt,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
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{
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OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(occ);
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DeviceClass *dc = DEVICE_CLASS(oc);
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device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
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&occ->parent_realize);
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device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
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cc->class_by_name = openrisc_cpu_class_by_name;
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cc->has_work = openrisc_cpu_has_work;
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cc->dump_state = openrisc_cpu_dump_state;
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cc->set_pc = openrisc_cpu_set_pc;
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cc->gdb_read_register = openrisc_cpu_gdb_read_register;
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cc->gdb_write_register = openrisc_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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dc->vmsd = &vmstate_openrisc_cpu;
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cc->sysemu_ops = &openrisc_sysemu_ops;
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#endif
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cc->gdb_num_core_regs = 32 + 3;
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cc->disas_set_info = openrisc_disas_set_info;
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cc->tcg_ops = &openrisc_tcg_ops;
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}
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/* Sort alphabetically by type name, except for "any". */
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static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
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return 1;
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} else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
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return -1;
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} else {
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return strcmp(name_a, name_b);
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}
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}
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static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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const char *typename;
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char *name;
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typename = object_class_get_name(oc);
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name = g_strndup(typename,
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strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
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qemu_printf(" %s\n", name);
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g_free(name);
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}
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void cpu_openrisc_list(void)
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{
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GSList *list;
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list = object_class_get_list(TYPE_OPENRISC_CPU, false);
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list = g_slist_sort(list, openrisc_cpu_list_compare);
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qemu_printf("Available CPUs:\n");
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g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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#define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_OPENRISC_CPU, \
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.instance_init = initfn, \
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.name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo openrisc_cpus_type_infos[] = {
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{ /* base class should be registered first */
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.name = TYPE_OPENRISC_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(OpenRISCCPU),
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.instance_init = openrisc_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(OpenRISCCPUClass),
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.class_init = openrisc_cpu_class_init,
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},
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DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
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DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
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};
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DEFINE_TYPES(openrisc_cpus_type_infos)
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