d423baf9b4
Changed hash32 address translation to use the supplied mmu_idx, instead of using what was stored in the msr, for parity purposes (radix64 already uses that) and for conceptual correctness, all the relevant functions should always use the supplied mmu_idx, as there are no guarantees that the mmu_idx stored in the CPU variable will not desync. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210706150316.21005-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
#ifndef MMU_HASH32_H
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#define MMU_HASH32_H
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#ifndef CONFIG_USER_ONLY
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hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
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bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
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bool guest_visible);
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/*
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* Segment register definitions
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*/
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#define SR32_T 0x80000000
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#define SR32_KS 0x40000000
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#define SR32_KP 0x20000000
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#define SR32_NX 0x10000000
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#define SR32_VSID 0x00ffffff
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/*
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* Block Address Translation (BAT) definitions
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*/
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#define BATU32_BEPIU 0xf0000000
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#define BATU32_BEPIL 0x0ffe0000
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#define BATU32_BEPI 0xfffe0000
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#define BATU32_BL 0x00001ffc
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#define BATU32_VS 0x00000002
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#define BATU32_VP 0x00000001
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#define BATL32_BRPN 0xfffe0000
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#define BATL32_WIMG 0x00000078
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#define BATL32_PP 0x00000003
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/* PowerPC 601 has slightly different BAT registers */
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#define BATU32_601_KS 0x00000008
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#define BATU32_601_KP 0x00000004
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#define BATU32_601_PP 0x00000003
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#define BATL32_601_V 0x00000040
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#define BATL32_601_BL 0x0000003f
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/*
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* Hash page table definitions
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*/
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#define SDR_32_HTABORG 0xFFFF0000UL
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#define SDR_32_HTABMASK 0x000001FFUL
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_32 8
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#define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
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#define HPTE32_V_VALID 0x80000000
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#define HPTE32_V_VSID 0x7fffff80
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#define HPTE32_V_SECONDARY 0x00000040
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#define HPTE32_V_API 0x0000003f
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#define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf))
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#define HPTE32_R_RPN 0xfffff000
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#define HPTE32_R_R 0x00000100
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#define HPTE32_R_C 0x00000080
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#define HPTE32_R_W 0x00000040
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#define HPTE32_R_I 0x00000020
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#define HPTE32_R_M 0x00000010
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#define HPTE32_R_G 0x00000008
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#define HPTE32_R_WIMG 0x00000078
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#define HPTE32_R_PP 0x00000003
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static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu)
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{
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return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG;
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}
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static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
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{
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return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF;
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}
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static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
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hwaddr pte_offset)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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return ldl_phys(CPU(cpu)->as, base + pte_offset);
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}
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static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
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hwaddr pte_offset)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
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}
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static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
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hwaddr pte_offset, target_ulong pte0)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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stl_phys(CPU(cpu)->as, base + pte_offset, pte0);
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}
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static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
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hwaddr pte_offset, target_ulong pte1)
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{
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target_ulong base = ppc_hash32_hpt_base(cpu);
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stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
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}
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typedef struct {
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uint32_t pte0, pte1;
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} ppc_hash_pte32_t;
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#endif /* CONFIG_USER_ONLY */
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#endif /* MMU_HASH32_H */
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