20e2d04e66
Implement instructions plxssp/pstxssp and port lxssp/stxssp to decode tree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-49-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
229 lines
9.4 KiB
Plaintext
229 lines
9.4 KiB
Plaintext
#
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# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
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#
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# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# Format MLS:D and 8LS:D
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&PLS_D rt ra si:int64_t r:bool
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%pls_si 32:s18 0:16
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@PLS_D ...... .. ... r:1 .. .................. \
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...... rt:5 ra:5 ................ \
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&PLS_D si=%pls_si
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@8LS_D_TSX ...... .. . .. r:1 .. .................. \
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..... rt:6 ra:5 ................ \
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&PLS_D si=%pls_si
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%rt_tsxp 21:1 22:4 !function=times_2
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@8LS_D_TSXP ...... .. . .. r:1 .. .................. \
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...... ..... ra:5 ................ \
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&PLS_D si=%pls_si rt=%rt_tsxp
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@8LS_D ...... .. . .. r:1 .. .................. \
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...... rt:5 ra:5 ................ \
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&PLS_D si=%pls_si
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# Format 8RR:D
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%8rr_si 32:s16 0:16
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%8rr_xt 16:1 21:5
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&8RR_D_IX xt ix si
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@8RR_D_IX ...... .. .... .. .. ................ \
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...... ..... ... ix:1 . ................ \
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&8RR_D_IX si=%8rr_si xt=%8rr_xt
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&8RR_D xt si:int32_t
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@8RR_D ...... .. .... .. .. ................ \
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...... ..... .... . ................ \
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&8RR_D si=%8rr_si xt=%8rr_xt
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# Format 8RR:XX4
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%8rr_xx_xt 0:1 21:5
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%8rr_xx_xa 2:1 16:5
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%8rr_xx_xb 1:1 11:5
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%8rr_xx_xc 3:1 6:5
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&8RR_XX4 xt xa xb xc
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@8RR_XX4 ........ ........ ........ ........ \
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...... ..... ..... ..... ..... .. .... \
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&8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
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&8RR_XX4_imm xt xa xb xc imm
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@8RR_XX4_imm ........ ........ ........ imm:8 \
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...... ..... ..... ..... ..... .. .... \
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&8RR_XX4_imm xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
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&8RR_XX4_uim3 xt xa xb xc uim3
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@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \
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...... ..... ..... ..... ..... .. .... \
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&8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
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### Fixed-Point Load Instructions
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PLBZ 000001 10 0--.-- .................. \
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100010 ..... ..... ................ @PLS_D
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PLHZ 000001 10 0--.-- .................. \
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101000 ..... ..... ................ @PLS_D
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PLHA 000001 10 0--.-- .................. \
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101010 ..... ..... ................ @PLS_D
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PLWZ 000001 10 0--.-- .................. \
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100000 ..... ..... ................ @PLS_D
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PLWA 000001 00 0--.-- .................. \
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101001 ..... ..... ................ @PLS_D
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PLD 000001 00 0--.-- .................. \
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111001 ..... ..... ................ @PLS_D
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PLQ 000001 00 0--.-- .................. \
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111000 ..... ..... ................ @PLS_D
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### Fixed-Point Store Instructions
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PSTW 000001 10 0--.-- .................. \
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100100 ..... ..... ................ @PLS_D
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PSTB 000001 10 0--.-- .................. \
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100110 ..... ..... ................ @PLS_D
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PSTH 000001 10 0--.-- .................. \
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101100 ..... ..... ................ @PLS_D
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PSTD 000001 00 0--.-- .................. \
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111101 ..... ..... ................ @PLS_D
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PSTQ 000001 00 0--.-- .................. \
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111100 ..... ..... ................ @PLS_D
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### Fixed-Point Arithmetic Instructions
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PADDI 000001 10 0--.-- .................. \
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001110 ..... ..... ................ @PLS_D
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### Float-Point Load and Store Instructions
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PLFS 000001 10 0--.-- .................. \
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110000 ..... ..... ................ @PLS_D
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PLFD 000001 10 0--.-- .................. \
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110010 ..... ..... ................ @PLS_D
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PSTFS 000001 10 0--.-- .................. \
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110100 ..... ..... ................ @PLS_D
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PSTFD 000001 10 0--.-- .................. \
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110110 ..... ..... ................ @PLS_D
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### Prefixed No-operation Instruction
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@PNOP 000001 11 0000-- 000000000000000000 \
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................................
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{
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[
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## Invalid suffixes: Branch instruction
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# bc[l][a]
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INVALID ................................ \
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010000-------------------------- @PNOP
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# b[l][a]
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INVALID ................................ \
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010010-------------------------- @PNOP
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# bclr[l]
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INVALID ................................ \
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010011---------------0000010000- @PNOP
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# bcctr[l]
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INVALID ................................ \
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010011---------------1000010000- @PNOP
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# bctar[l]
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INVALID ................................ \
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010011---------------1000110000- @PNOP
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## Invalid suffixes: rfebb
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INVALID ................................ \
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010011---------------0010010010- @PNOP
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## Invalid suffixes: context synchronizing other than isync
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# sc
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INVALID ................................ \
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010001------------------------1- @PNOP
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# scv
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INVALID ................................ \
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010001------------------------01 @PNOP
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# rfscv
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INVALID ................................ \
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010011---------------0001010010- @PNOP
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# rfid
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INVALID ................................ \
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010011---------------0000010010- @PNOP
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# hrfid
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INVALID ................................ \
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010011---------------0100010010- @PNOP
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# urfid
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INVALID ................................ \
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010011---------------0100110010- @PNOP
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# stop
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INVALID ................................ \
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010011---------------0101110010- @PNOP
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# mtmsr w/ L=0
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INVALID ................................ \
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011111---------0-----0010010010- @PNOP
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# mtmsrd w/ L=0
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INVALID ................................ \
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011111---------0-----0010110010- @PNOP
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## Invalid suffixes: Service Processor Attention
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INVALID ................................ \
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000000----------------100000000- @PNOP
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]
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## Valid suffixes
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PNOP ................................ \
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-------------------------------- @PNOP
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}
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### VSX instructions
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PLXSD 000001 00 0--.-- .................. \
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101010 ..... ..... ................ @8LS_D
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PSTXSD 000001 00 0--.-- .................. \
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101110 ..... ..... ................ @8LS_D
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PLXSSP 000001 00 0--.-- .................. \
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101011 ..... ..... ................ @8LS_D
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PSTXSSP 000001 00 0--.-- .................. \
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101111 ..... ..... ................ @8LS_D
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PLXV 000001 00 0--.-- .................. \
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11001 ...... ..... ................ @8LS_D_TSX
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PSTXV 000001 00 0--.-- .................. \
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11011 ...... ..... ................ @8LS_D_TSX
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PLXVP 000001 00 0--.-- .................. \
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111010 ..... ..... ................ @8LS_D_TSXP
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PSTXVP 000001 00 0--.-- .................. \
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111110 ..... ..... ................ @8LS_D_TSXP
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XXEVAL 000001 01 0000 -- ---------- ........ \
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100010 ..... ..... ..... ..... 01 .... @8RR_XX4_imm
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XXSPLTIDP 000001 01 0000 -- -- ................ \
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100000 ..... 0010 . ................ @8RR_D
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XXSPLTIW 000001 01 0000 -- -- ................ \
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100000 ..... 0011 . ................ @8RR_D
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XXSPLTI32DX 000001 01 0000 -- -- ................ \
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100000 ..... 000 .. ................ @8RR_D_IX
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XXBLENDVD 000001 01 0000 -- ------------------ \
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100001 ..... ..... ..... ..... 11 .... @8RR_XX4
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XXBLENDVW 000001 01 0000 -- ------------------ \
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100001 ..... ..... ..... ..... 10 .... @8RR_XX4
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XXBLENDVH 000001 01 0000 -- ------------------ \
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100001 ..... ..... ..... ..... 01 .... @8RR_XX4
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XXBLENDVB 000001 01 0000 -- ------------------ \
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100001 ..... ..... ..... ..... 00 .... @8RR_XX4
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XXPERMX 000001 01 0000 -- --------------- ... \
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100010 ..... ..... ..... ..... 00 .... @8RR_XX4_uim3
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