679f4f8b17
The unplug protocol is necessary to support PV drivers in the guest: the drivers expect to be able to "unplug" emulated disks and nics before initializing the Xen PV interfaces. It is responsibility of the guest to make sure that the unplug is done before the emulated devices or the PV interface start to be used. We use pci_for_each_device to walk the PCI bus, identify the devices and disks that we want to disable and dynamically unplug them. Changes in v2: - use PCI_CLASS constants; - replace pci_unplug_device with qdev_unplug; - do not import hw/ide/internal.h in xen_platform.c; Changes in v3: - introduce piix3-ide-xen, that support hot-unplug; - move the unplug code to hw/ide/piix.c; - just call qdev_unplug from xen_platform.c to unplug the IDE disks; Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
247 lines
7.0 KiB
C
247 lines
7.0 KiB
C
/*
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* QEMU IDE Emulation: PCI PIIX3/4 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) {
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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}
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}
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static void bmdma_map(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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int i;
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
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register_ioport_read(addr, 4, 1, bmdma_readb, bm);
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iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
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ioport_register(&bm->addr_ioport);
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addr += 8;
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}
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}
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static void piix3_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND] = 0x00;
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND + 1] = 0x00;
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/* TODO: use pci_set_word */
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pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
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pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
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pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
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}
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static void pci_piix_init_ports(PCIIDEState *d) {
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int i;
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struct {
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int iobase;
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int iobase2;
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int isairq;
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} port_info[] = {
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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for (i = 0; i < 2; i++) {
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ide_bus_new(&d->bus[i], &d->dev.qdev, i);
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ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
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ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i]);
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d->bmdma[i].bus = &d->bus[i];
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qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
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&d->bmdma[i].dma);
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}
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}
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static int pci_piix_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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uint8_t *pci_conf = d->dev.config;
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pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
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qemu_register_reset(piix3_reset, d);
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pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
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vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
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pci_piix_init_ports(d);
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return 0;
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}
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static int pci_piix3_xen_ide_unplug(DeviceState *dev)
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{
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PCIDevice *pci_dev;
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PCIIDEState *pci_ide;
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DriveInfo *di;
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int i = 0;
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pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
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pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
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for (; i < 3; i++) {
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di = drive_get_by_index(IF_IDE, i);
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if (di != NULL && di->bdrv != NULL && !di->bdrv->removable) {
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DeviceState *ds = bdrv_get_attached(di->bdrv);
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if (ds) {
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bdrv_detach(di->bdrv, ds);
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}
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bdrv_close(di->bdrv);
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pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
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drive_put_ref(di);
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}
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}
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qdev_reset_all(&(pci_ide->dev.qdev));
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return 0;
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}
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PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
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dev->qdev.info->unplug = pci_piix3_xen_ide_unplug;
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
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PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix3-ide");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
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PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix4-ide");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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static PCIDeviceInfo piix_ide_info[] = {
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{
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.qdev.name = "piix3-ide",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.no_hotplug = 1,
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.init = pci_piix_ide_initfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
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.class_id = PCI_CLASS_STORAGE_IDE,
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},{
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.qdev.name = "piix3-ide-xen",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.init = pci_piix_ide_initfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
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.class_id = PCI_CLASS_STORAGE_IDE,
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},{
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.qdev.name = "piix4-ide",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.no_hotplug = 1,
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.init = pci_piix_ide_initfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371AB,
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.class_id = PCI_CLASS_STORAGE_IDE,
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},{
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/* end of list */
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}
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};
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static void piix_ide_register(void)
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{
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pci_qdev_register_many(piix_ide_info);
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}
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device_init(piix_ide_register);
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