qemu-e2k/hw/ssi
Peter Maydell 1862198702 migration: Remove load_state_old and minimum_version_id_old
There are no longer any VMStateDescription structs in the tree which
use the load_state_old support for custom handling of incoming
migration from very old QEMU.  Remove the mechanism entirely.

This includes removing one stray useless setting of
minimum_version_id_old in a VMStateDescription with no load_state_old
function, which crept in after the global weeding-out of them in
commit 17e3134061.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220215175705.3846411-1-peter.maydell@linaro.org>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-03-02 18:20:45 +00:00
..
aspeed_smc.c aspeed/smc: Add an address mask on segment registers 2022-02-26 18:40:51 +01:00
imx_spi.c hw/ssi: imx_spi: Correct tx and rx fifo endianness 2021-02-02 17:00:55 +00:00
Kconfig hw/ssi: Add SiFive SPI controller support 2021-03-04 09:43:29 -05:00
meson.build hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller 2022-01-28 14:29:46 +00:00
mss-spi.c
npcm7xx_fiu.c hw/*: Use type casting for SysBusDevice in NPCM7XX 2021-01-12 21:19:02 +00:00
omap_spi.c
pl022.c hw/ssi: Rename SSI 'slave' as 'peripheral' 2020-12-10 12:15:03 -05:00
sifive_spi.c Do not include sysemu/sysemu.h if it's not really necessary 2021-05-02 17:24:50 +02:00
ssi.c qbus: Rename qbus_create() to qbus_new() 2021-09-30 13:44:08 +01:00
stm32f2xx_spi.c
trace-events hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer 2020-10-08 15:24:32 +01:00
trace.h
xilinx_spi.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
xilinx_spips.c hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips 2021-03-10 13:54:51 +00:00
xlnx-versal-ospi.c migration: Remove load_state_old and minimum_version_id_old 2022-03-02 18:20:45 +00:00