4a295211f7
This infrastructure will be reused for CXL RAS error injection in patches that follow. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230302133709.30373-8-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Fan Ni <fan.ni@samsung.com>
25 lines
614 B
C
25 lines
614 B
C
#ifndef HW_PCI_PCI_INTERNAL_H
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#define HW_PCI_PCI_INTERNAL_H
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#include "qemu/queue.h"
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typedef struct {
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uint16_t class;
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const char *desc;
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const char *fw_name;
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uint16_t fw_ign_bits;
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} pci_class_desc;
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typedef QLIST_HEAD(, PCIHostState) PCIHostStateList;
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extern PCIHostStateList pci_host_bridges;
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const pci_class_desc *get_class_desc(int class);
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PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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int pcie_aer_parse_error_string(const char *error_name,
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uint32_t *status, bool *correctable);
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#endif
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