Román Cárdenas a7472560ca riscv: Fix SiFive E CLINT clock frequency ... If you check the manual of SiFive E310 (https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf), you can see in Figure 1 that the CLINT is connected to the real time clock, which also feeds the AON peripheral (they share the same clock). In page 43, the docs also say that the timer registers of the CLINT count ticks from the rtcclk. I am currently playing with bare metal applications both in QEMU and a physical SiFive E310 board and I confirm that the CLINT clock in the physical board runs at 32.768 kHz. In QEMU, the same app produces a completely different outcome, as sometimes a new CLINT interrupt is triggered before finishing other tasks. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1978 Signed-off-by: Rom\ufffd\ufffdn C\ufffd\ufffdrdenas <rcardenas.rod@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231117082840.55705-1-rcardenas.rod@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-22 13:57:19 +10:00
..
boot.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
Kconfig
meson.build
microchip_pfsoc.c
numa.c
opentitan.c
riscv_hart.c
shakti_c.c
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c
spike.c
virt-acpi-build.c
virt.c	hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt()	2023-11-22 13:55:07 +10:00