6ac0d8d44c
PIIX4 has disable_s3 and disable_s4 properties to enable or disable PM functions. Add such properties to the ICH9 chipset as well for the Q35 machine type. S3 / S4 are not guaranteed to always work (needs work in the guest as well as QEMU for things to work properly), and disabling advertising of these features ensures guests don't go into zombie state if something isn't working right. The defaults are kept the same as in PIIX4: both S3 and S4 are enabled by default. These can be disabled via the cmdline: ... -global ICH9-LPC.disable_s3=1 -global ICH9-LPC.disable_s4=1 Note: some guests can fake hibernation by writing a hibernate image and doing a shutdown instead of S4 if S4 isn't available; there's nothing we can do guests to stop doing this, and this patch can't affect that functionality. Signed-off-by: Amit Shah <amit.shah@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* QEMU GMCH/ICH9 LPC PM Emulation
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#ifndef HW_ACPI_ICH9_H
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#define HW_ACPI_ICH9_H
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/acpi/memory_hotplug.h"
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#include "hw/acpi/acpi_dev_interface.h"
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typedef struct ICH9LPCPMRegs {
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/*
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* In ich9 spec says that pm1_cnt register is 32bit width and
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* that the upper 16bits are reserved and unused.
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* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
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*/
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ACPIREGS acpi_regs;
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MemoryRegion io;
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MemoryRegion io_gpe;
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MemoryRegion io_smi;
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uint32_t smi_en;
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uint32_t smi_sts;
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qemu_irq irq; /* SCI */
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uint32_t pm_io_base;
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Notifier powerdown_notifier;
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AcpiCpuHotplug gpe_cpu;
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MemHotplugState acpi_memory_hotplug;
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uint8_t disable_s3;
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uint8_t disable_s4;
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uint8_t s4_val;
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} ICH9LPCPMRegs;
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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qemu_irq sci_irq);
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void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
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extern const VMStateDescription vmstate_ich9_pm;
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void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp);
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void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp);
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void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list);
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#endif /* HW_ACPI_ICH9_H */
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