390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* S/390 helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/gdbstub.h"
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#include "qemu/timer.h"
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#include "exec/exec-all.h"
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#include "hw/s390x/ioinst.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#endif
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//#define DEBUG_S390
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//#define DEBUG_S390_STDOUT
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifndef CONFIG_USER_ONLY
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void s390x_tod_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_TOD;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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void s390x_cpu_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_CPUTIMER;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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#endif
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S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp)
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{
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static bool features_parsed;
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char *name, *features;
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const char *typename;
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ObjectClass *oc;
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CPUClass *cc;
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name = g_strdup(cpu_model);
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features = strchr(name, ',');
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if (features) {
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features[0] = 0;
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features++;
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}
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oc = cpu_class_by_name(TYPE_S390_CPU, name);
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if (!oc) {
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error_setg(errp, "Unknown CPU definition \'%s\'", name);
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g_free(name);
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return NULL;
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}
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typename = object_class_get_name(oc);
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if (!features_parsed) {
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features_parsed = true;
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cc = CPU_CLASS(oc);
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cc->parse_features(typename, features, errp);
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}
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g_free(name);
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if (*errp) {
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return NULL;
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}
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return S390_CPU(CPU(object_new(typename)));
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}
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S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp)
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{
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S390CPU *cpu;
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Error *err = NULL;
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cpu = cpu_s390x_create(cpu_model, &err);
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if (err != NULL) {
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goto out;
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}
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object_property_set_int(OBJECT(cpu), id, "id", &err);
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if (err != NULL) {
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goto out;
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}
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object_property_set_bool(OBJECT(cpu), true, "realized", &err);
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out:
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if (err) {
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error_propagate(errp, err);
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object_unref(OBJECT(cpu));
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cpu = NULL;
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}
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return cpu;
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}
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#ifndef CONFIG_USER_ONLY
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong raddr;
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int prot;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
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return -1;
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}
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return raddr;
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}
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hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
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{
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hwaddr phys_addr;
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target_ulong page;
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page = vaddr & TARGET_PAGE_MASK;
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phys_addr = cpu_get_phys_page_debug(cs, page);
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phys_addr += (vaddr & ~TARGET_PAGE_MASK);
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return phys_addr;
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}
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void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
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{
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uint64_t old_mask = env->psw.mask;
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env->psw.addr = addr;
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env->psw.mask = mask;
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if (tcg_enabled()) {
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env->cc_op = (mask >> 44) & 3;
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}
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if ((old_mask ^ mask) & PSW_MASK_PER) {
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s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
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}
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if (mask & PSW_MASK_WAIT) {
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S390CPU *cpu = s390_env_get_cpu(env);
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if (s390_cpu_halt(cpu) == 0) {
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#ifndef CONFIG_USER_ONLY
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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#endif
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}
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}
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}
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uint64_t get_psw_mask(CPUS390XState *env)
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{
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uint64_t r = env->psw.mask;
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if (tcg_enabled()) {
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env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
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env->cc_vr);
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r &= ~PSW_MASK_CC;
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assert(!(env->cc_op & ~3));
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r |= (uint64_t)env->cc_op << 44;
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}
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return r;
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}
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LowCore *cpu_map_lowcore(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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LowCore *lowcore;
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hwaddr len = sizeof(LowCore);
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lowcore = cpu_physical_memory_map(env->psa, &len, 1);
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if (len < sizeof(LowCore)) {
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cpu_abort(CPU(cpu), "Could not map lowcore\n");
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}
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return lowcore;
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}
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void cpu_unmap_lowcore(LowCore *lowcore)
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{
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cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
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}
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void do_restart_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->restart_new_psw.mask);
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addr = be64_to_cpu(lowcore->restart_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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}
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void s390_cpu_recompute_watchpoints(CPUState *cs)
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{
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const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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/* We are called when the watchpoints have changed. First
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remove them all. */
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cpu_watchpoint_remove_all(cs, BP_CPU);
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/* Return if PER is not enabled */
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if (!(env->psw.mask & PSW_MASK_PER)) {
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return;
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}
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/* Return if storage-alteration event is not enabled. */
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if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
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return;
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}
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if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
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/* We can't create a watchoint spanning the whole memory range, so
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split it in two parts. */
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cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
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cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
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} else if (env->cregs[10] > env->cregs[11]) {
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/* The address range loops, create two watchpoints. */
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cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
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wp_flags, NULL);
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cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
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} else {
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/* Default case, create a single watchpoint. */
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cpu_watchpoint_insert(cs, env->cregs[10],
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env->cregs[11] - env->cregs[10] + 1,
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wp_flags, NULL);
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}
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}
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#endif /* CONFIG_USER_ONLY */
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void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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int i;
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if (env->cc_op > 3) {
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cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
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env->psw.mask, env->psw.addr, cc_name(env->cc_op));
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} else {
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cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
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env->psw.mask, env->psw.addr, env->cc_op);
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}
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for (i = 0; i < 16; i++) {
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cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
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if ((i % 4) == 3) {
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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}
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}
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for (i = 0; i < 16; i++) {
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cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
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if ((i % 4) == 3) {
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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}
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}
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for (i = 0; i < 32; i++) {
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cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
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env->vregs[i][0].ll, env->vregs[i][1].ll);
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cpu_fprintf(f, (i % 2) ? "\n" : " ");
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}
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < 16; i++) {
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cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
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if ((i % 4) == 3) {
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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}
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}
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#endif
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#ifdef DEBUG_INLINE_BRANCHES
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for (i = 0; i < CC_OP_MAX; i++) {
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cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
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inline_branch_miss[i], inline_branch_hit[i]);
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}
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#endif
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cpu_fprintf(f, "\n");
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}
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const char *cc_name(enum cc_op cc_op)
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{
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static const char * const cc_names[] = {
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[CC_OP_CONST0] = "CC_OP_CONST0",
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[CC_OP_CONST1] = "CC_OP_CONST1",
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[CC_OP_CONST2] = "CC_OP_CONST2",
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[CC_OP_CONST3] = "CC_OP_CONST3",
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[CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
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[CC_OP_STATIC] = "CC_OP_STATIC",
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[CC_OP_NZ] = "CC_OP_NZ",
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[CC_OP_LTGT_32] = "CC_OP_LTGT_32",
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[CC_OP_LTGT_64] = "CC_OP_LTGT_64",
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[CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
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[CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
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[CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
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[CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
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[CC_OP_ADD_64] = "CC_OP_ADD_64",
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[CC_OP_ADDU_64] = "CC_OP_ADDU_64",
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[CC_OP_ADDC_64] = "CC_OP_ADDC_64",
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[CC_OP_SUB_64] = "CC_OP_SUB_64",
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[CC_OP_SUBU_64] = "CC_OP_SUBU_64",
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[CC_OP_SUBB_64] = "CC_OP_SUBB_64",
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[CC_OP_ABS_64] = "CC_OP_ABS_64",
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[CC_OP_NABS_64] = "CC_OP_NABS_64",
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[CC_OP_ADD_32] = "CC_OP_ADD_32",
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[CC_OP_ADDU_32] = "CC_OP_ADDU_32",
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[CC_OP_ADDC_32] = "CC_OP_ADDC_32",
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[CC_OP_SUB_32] = "CC_OP_SUB_32",
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[CC_OP_SUBU_32] = "CC_OP_SUBU_32",
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[CC_OP_SUBB_32] = "CC_OP_SUBB_32",
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[CC_OP_ABS_32] = "CC_OP_ABS_32",
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[CC_OP_NABS_32] = "CC_OP_NABS_32",
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[CC_OP_COMP_32] = "CC_OP_COMP_32",
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[CC_OP_COMP_64] = "CC_OP_COMP_64",
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[CC_OP_TM_32] = "CC_OP_TM_32",
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[CC_OP_TM_64] = "CC_OP_TM_64",
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[CC_OP_NZ_F32] = "CC_OP_NZ_F32",
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[CC_OP_NZ_F64] = "CC_OP_NZ_F64",
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[CC_OP_NZ_F128] = "CC_OP_NZ_F128",
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[CC_OP_ICM] = "CC_OP_ICM",
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[CC_OP_SLA_32] = "CC_OP_SLA_32",
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[CC_OP_SLA_64] = "CC_OP_SLA_64",
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[CC_OP_FLOGR] = "CC_OP_FLOGR",
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};
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return cc_names[cc_op];
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}
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