5fcc499ee3
Once a read or write reaches a CXL type 3 device, the HDM decoders on the device are used to establish the Device Physical Address which should be accessed. These functions peform the required maths and then use a device specific address space to access the hostmem->mr to fullfil the actual operation. Note that failed writes are silent, but failed reads return poison. Note this is based loosely on: https://lore.kernel.org/qemu-devel/20200817161853.593247-6-f4bug@amsat.org/ [RFC PATCH 0/9] hw/misc: Add support for interleaved memory accesses Only lightly tested so far. More complex test cases yet to be written. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220429144110.25167-33-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
269 lines
11 KiB
C
269 lines
11 KiB
C
/*
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* QEMU CXL Devices
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*
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* Copyright (c) 2020 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_DEVICE_H
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#define CXL_DEVICE_H
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#include "hw/register.h"
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/*
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* The following is how a CXL device's Memory Device registers are laid out.
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* The only requirement from the spec is that the capabilities array and the
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* capability headers start at offset 0 and are contiguously packed. The headers
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* themselves provide offsets to the register fields. For this emulation, the
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* actual registers * will start at offset 0x80 (m == 0x80). No secondary
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* mailbox is implemented which means that the offset of the start of the
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* mailbox payload (n) is given by
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* n = m + sizeof(mailbox registers) + sizeof(device registers).
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*
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* +---------------------------------+
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* | |
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* | Memory Device Registers |
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* | |
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* n + PAYLOAD_SIZE_MAX -----------------------------------
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* ^ | |
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* | | |
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* | | |
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* | | |
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* | | |
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* | | Mailbox Payload |
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* | | |
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* | | |
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* | | |
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* n -----------------------------------
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* ^ | Mailbox Registers |
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* | | |
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* | -----------------------------------
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* | | |
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* | | Device Registers |
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* | | |
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* m ---------------------------------->
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* ^ | Memory Device Capability Header|
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* | -----------------------------------
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* | | Mailbox Capability Header |
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* | -----------------------------------
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* | | Device Capability Header |
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* | -----------------------------------
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* | | Device Cap Array Register |
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* 0 +---------------------------------+
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*
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*/
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#define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */
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#define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */
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#define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */
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#define CXL_CAPS_SIZE \
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(CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
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#define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
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#define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */
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#define CXL_MAILBOX_REGISTERS_OFFSET \
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(CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
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#define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */
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#define CXL_MAILBOX_PAYLOAD_SHIFT 11
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#define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
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#define CXL_MAILBOX_REGISTERS_LENGTH \
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(CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
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#define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
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(CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
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#define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
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#define CXL_MMIO_SIZE \
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(CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \
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CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
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typedef struct cxl_device_state {
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MemoryRegion device_registers;
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/* mmio for device capabilities array - 8.2.8.2 */
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MemoryRegion device;
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MemoryRegion memory_device;
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struct {
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MemoryRegion caps;
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union {
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uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4];
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uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8];
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};
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};
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/* mmio for the mailbox registers 8.2.8.4 */
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struct {
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MemoryRegion mailbox;
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uint16_t payload_size;
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union {
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uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
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uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
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uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
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uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
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};
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struct cel_log {
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uint16_t opcode;
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uint16_t effect;
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} cel_log[1 << 16];
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size_t cel_size;
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};
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struct {
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bool set;
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uint64_t last_set;
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uint64_t host_set;
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} timestamp;
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/* memory region for persistent memory, HDM */
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uint64_t pmem_size;
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} CXLDeviceState;
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/* Initialize the register block for a device */
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void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev);
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/* Set up default values for the register block */
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void cxl_device_register_init_common(CXLDeviceState *dev);
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/*
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* CXL 2.0 - 8.2.8.1 including errata F4
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* Documented as a 128 bit register, but 64 bit accesses and the second
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* 64 bits are currently reserved.
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*/
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REG64(CXL_DEV_CAP_ARRAY, 0) /* Documented as 128 bit register but 64 byte accesses */
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FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
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FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
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FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
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/*
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* Helper macro to initialize capability headers for CXL devices.
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*
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* In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says:
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* > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
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* > is the maximum access size allowed for these registers. If this rule is not
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* > followed, the behavior is undefined
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*
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* CXL 2.0 Errata F4 states futher that the layouts in the specification are
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* shown as greater than 128 bits, but implementations are expected to
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* use any size of access up to 64 bits.
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*
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* Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple
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* access to be used for a register up to 64 bits.
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*/
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#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \
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REG32(CXL_DEV_##n##_CAP_HDR0, offset) \
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FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \
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FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
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REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \
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FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \
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REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \
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FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
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CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
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CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
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CXL_DEVICE_CAP_REG_SIZE)
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CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
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CXL_DEVICE_CAP_HDR1_OFFSET +
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CXL_DEVICE_CAP_REG_SIZE * 2)
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int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate);
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void cxl_process_mailbox(CXLDeviceState *cxl_dstate);
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#define cxl_device_cap_init(dstate, reg, cap_id) \
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do { \
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uint32_t *cap_hdrs = dstate->caps_reg_state32; \
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int which = R_CXL_DEV_##reg##_CAP_HDR0; \
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cap_hdrs[which] = \
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FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \
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CAP_ID, cap_id); \
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cap_hdrs[which] = FIELD_DP32( \
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cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \
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cap_hdrs[which + 1] = \
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FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \
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CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \
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cap_hdrs[which + 2] = \
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FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \
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CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \
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} while (0)
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/* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */
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REG32(CXL_DEV_MAILBOX_CAP, 0)
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FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
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FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
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FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
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FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
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/* CXL 2.0 8.2.8.4.4 Mailbox Control Register */
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REG32(CXL_DEV_MAILBOX_CTRL, 4)
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FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
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FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
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FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
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/* CXL 2.0 8.2.8.4.5 Command Register */
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REG64(CXL_DEV_MAILBOX_CMD, 8)
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FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
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FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
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FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
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/* CXL 2.0 8.2.8.4.6 Mailbox Status Register */
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REG64(CXL_DEV_MAILBOX_STS, 0x10)
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FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
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FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
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FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
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/* CXL 2.0 8.2.8.4.7 Background Command Status Register */
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REG64(CXL_DEV_BG_CMD_STS, 0x18)
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FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
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FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
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FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
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FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
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/* CXL 2.0 8.2.8.4.8 Command Payload Registers */
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REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
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REG64(CXL_MEM_DEV_STS, 0)
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FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
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FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
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FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
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FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
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FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
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struct CXLType3Dev {
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/* Private */
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PCIDevice parent_obj;
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/* Properties */
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HostMemoryBackend *hostmem;
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HostMemoryBackend *lsa;
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/* State */
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AddressSpace hostmem_as;
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CXLComponentState cxl_cstate;
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CXLDeviceState cxl_dstate;
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};
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#define TYPE_CXL_TYPE3 "cxl-type3"
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OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
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struct CXLType3Class {
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/* Private */
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PCIDeviceClass parent_class;
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/* public */
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uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
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uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
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uint64_t offset);
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void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
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uint64_t offset);
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};
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MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs);
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MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
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unsigned size, MemTxAttrs attrs);
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#endif
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